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| author | Tim Newsome <tim@sifive.com> | 2017-02-07 09:07:59 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-02-07 09:07:59 -0800 |
| commit | daaf28f7296c0a5f5c90fe6646a4f8a73a720af5 (patch) | |
| tree | 2c00ae49b5eeadbd189d20a63fc29db25906cc39 | |
| parent | 9e012462f53113dc9ed00d7fbb89aeafeb9b89e9 (diff) | |
| parent | 71f64bfe4eb2d4d1b0795b71db555fd825593ab3 (diff) | |
| download | spike-daaf28f7296c0a5f5c90fe6646a4f8a73a720af5.zip spike-daaf28f7296c0a5f5c90fe6646a4f8a73a720af5.tar.gz spike-daaf28f7296c0a5f5c90fe6646a4f8a73a720af5.tar.bz2 | |
Merge pull request #83 from bacam/gdb-protocol-fixes
Gdb protocol fixes
| -rw-r--r-- | riscv/gdbserver.cc | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 7e83c49..79284eb 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -592,12 +592,16 @@ class register_read_op_t : public operation_t switch (step) { case 0: if (reg >= REG_XPR0 && reg <= REG_XPR31) { + unsigned int i = 0; + if (reg == S0) { + gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH)); + } if (gs.xlen == 32) { - gs.dr_write32(0, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); + gs.dr_write32(i++, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); } else { - gs.dr_write32(0, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); + gs.dr_write32(i++, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); } - gs.dr_write_jump(1); + gs.dr_write_jump(i); } else if (reg == REG_PC) { gs.start_packet(); if (gs.xlen == 32) { @@ -1816,8 +1820,6 @@ void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet) processor_t *p = sim->get_core(0); add_operation(new register_write_op_t(*this, n, value)); - - return send_packet("OK"); } void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet) |