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author | Andrew Waterman <andrew@sifive.com> | 2017-01-07 17:56:22 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-01-07 17:56:22 -0800 |
commit | b387326dbc6b4bf2452191b6817529133ff362a5 (patch) | |
tree | 1e9d9bb15812b205de3e47884493bb95585a7f9f | |
parent | 51a0e1e9653320a162ced2cd0392ee9ef7558beb (diff) | |
download | spike-b387326dbc6b4bf2452191b6817529133ff362a5.zip spike-b387326dbc6b4bf2452191b6817529133ff362a5.tar.gz spike-b387326dbc6b4bf2452191b6817529133ff362a5.tar.bz2 |
Make SIP.STIP read-only
h/t Ron Minnich
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8
-rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f3764ae..75f4002 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -373,9 +373,10 @@ void processor_t::set_csr(int which, reg_t val) | SSTATUS_XS | SSTATUS_PUM; return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } - case CSR_SIP: - return set_csr(CSR_MIP, - (state.mip & ~state.mideleg) | (val & state.mideleg)); + case CSR_SIP: { + reg_t mask = MIP_SSIP; + return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); + } case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); |