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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 20:53:09 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 20:53:09 -0700 |
| commit | 693fc45eb8ccc3c9f84b898de3119a172e0776f5 (patch) | |
| tree | 9f4cd32af7266167ff78e8360ba2ce7ac8a5057e | |
| parent | 212d5198cfa79ac85a7b073c13cdf86e803614ee (diff) | |
| download | spike-693fc45eb8ccc3c9f84b898de3119a172e0776f5.zip spike-693fc45eb8ccc3c9f84b898de3119a172e0776f5.tar.gz spike-693fc45eb8ccc3c9f84b898de3119a172e0776f5.tar.bz2 | |
sim: declare cores as interrupt-controllers for clint
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index a2b5cd1..bdf55e2 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -276,6 +276,8 @@ void sim_t::make_dtb() " riscv,isa = \"" << procs[i]->isa_string << "\";\n" " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << CPU_HZ << ">;\n" + " interrupt-controller;\n" + " #interrupt-cells = <1>;\n" " };\n"; } reg_t membs = DRAM_BASE; |