remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIAN

the default target endian is always little endian:
- mmu::is_target_big_endian() return false
- sim_t::get_target_endianness() return memif_endianness_little
when RISCV_ENABLE_DUAL_ENDIAN  macro is undefined

3 files changed, 0 insertions, 14 deletions

diff --git a/fesvr/htif.h b/fesvr/htif.h
index 3cee25f..ca5b362 100644
--- a/fesvr/htif.h
+++ b/fesvr/htif.h
@@ -31,26 +31,18 @@ class htif_t : public chunked_memif_t
 
   template<typename T> inline T from_target(target_endian<T> n) const
   {
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
     memif_endianness_t endianness = get_target_endianness();
     assert(endianness == memif_endianness_little || endianness == memif_endianness_big);
 
     return endianness == memif_endianness_big? n.from_be() : n.from_le();
-#else
-    return n.from_le();
-#endif
   }
 
   template<typename T> inline target_endian<T> to_target(T n) const
   {
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
     memif_endianness_t endianness = get_target_endianness();
     assert(endianness == memif_endianness_little || endianness == memif_endianness_big);
 
     return endianness == memif_endianness_big? target_endian<T>::to_be(n) : target_endian<T>::to_le(n);
-#else
-    return target_endian<T>::to_le(n);
-#endif
   }
 
  protected:
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index be23a2e..c27410c 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -493,9 +493,7 @@ reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept {
   return 0
          | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
          | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
          | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0)
-#endif
          | 0;  // initial value for mstatus
 }
 
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 069e1b5..0000537 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -425,11 +425,7 @@ void sim_t::set_target_endianness(memif_endianness_t endianness)
 
 memif_endianness_t sim_t::get_target_endianness() const
 {
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
   return debug_mmu->is_target_big_endian()? memif_endianness_big : memif_endianness_little;
-#else
-  return memif_endianness_little;
-#endif
 }
 
 void sim_t::proc_reset(unsigned id)