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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-12 20:21:38 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-02-12 20:21:38 -0800 |
| commit | 74554e7d842df5c4d5b9fc1c7cc0f89ad3d5966e (patch) | |
| tree | b7a3bb08ae4addebe2a6b7c6858e3417c6cb4291 | |
| parent | fd0dbf46c3d9f8b005d35dfed79dbd4b4b0f974a (diff) | |
| download | spike-cycleh.zip spike-cycleh.tar.gz spike-cycleh.tar.bz2 | |
Implement cycleh/instreth CSRs for RV32cycleh
| -rw-r--r-- | riscv/processor.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 516a708..8cca490 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -565,6 +565,11 @@ reg_t processor_t::get_csr(int which) case CSR_MINSTRET: case CSR_MCYCLE: return state.minstret; + case CSR_INSTRETH: + case CSR_CYCLEH: + if (ctr_ok && xlen == 32) + return state.minstret >> 32; + break; case CSR_MINSTRETH: case CSR_MCYCLEH: if (xlen == 32) |