aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
12 daysMerge pull request #10 from jamin-aspeed/masterHEADmasterHao Wu1-3/+3
ast27x0: Fix Makefile to unconditionally set CC to support correct cross-compilation
13 daysast27x0: Fix Makefile to unconditionally set CC to support correct ↵Jamin Lin1-3/+3
cross-compilation The Makefile previously used CC ?= $(CROSS_COMPILE)gcc, but this is ineffective because make always sets the CC variable by default. As a result, the intended default for CC was ignored and cross-compilation could silently fail or misbehave. This patch removes the conditional assignment operator ?= for CC, OBJCOPY, and OBJDUMP, making them unconditionally defined from the CROSS_COMPILE prefix as done in other vbootrom subdirectories. This simplifies usage and makes the build work without requiring users to manually specify CC on the command line. Now users can simply run make without needing to export or override variables. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2025-07-16Merge pull request #9 from jamin-aspeed/ssp-tsp-resetHao Wu2-0/+18
ast27x0: Fix missing SCU module reset for SSP and TSP initialization
2025-07-14ast27x0: Fix missing SCU module reset for SSP and TSP initializationJamin Lin2-0/+18
Fix SSP and TSP boot failure caused by missing SCU reset control. This commit adds SCU modrst1/modrst2 reset logic to ssp_init() and tsp_init(). Without proper reset release, SSP and TSP CPUs stay in reset and cannot start. Also adds missing SCU register fields and reset bit definitions for SSP (BIT(30)) and TSP (BIT(9)). Fixes: 80768e4 ("ast27x0: Initialize and enable SSP/TSP using SCU with reserved- memory from DTB") Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2025-07-07Merge pull request #8 from jamin-aspeed/coprocessorHao Wu8-14/+487
ast27x0: Initialize and enable SSP/TSP using SCU
2025-07-07ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory from DTBJamin Lin8-14/+487
This commit adds support for bringing up the SSP and TSP co-processors on AST2700. The initialization and control logic are performed via SCU register programming. Memory layout for firmware regions is retrieved from reserved-memory nodes in the SPL device tree. Features included: - Add find_fmc_image() to locate FMC v2 image and extract payload range. - Load and validate SPL DTB located after FMC payload. - Parse reserved-memory nodes for SSP, TSP, ATF, OP-TEE, and IPC regions. - Define struct mem_region and reserved_mem_info for memory layout data. - Implement ssp_init() and ssp_enable() for SSP SCU setup and launch. - Implement tsp_init() and tsp_enable() for TSP SCU setup and launch. - Extend load_other_fit_images() to detect "sspfw" and "tspfw" images. - Enable SSP/TSP after loading firmware from FIT image. - Add SCU register definitions in struct ast2700_scu0. Note: DTB is only used to retrieve memory layout for reserved regions. The SSP and TSP initialization and activation are done via SCU registers. Code adapted from: https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/board/aspeed/ibex_ast2700/ssp_tsp.c Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2025-04-28Merge pull request #7 from jamin-aspeed/issues-6Hao Wu2-4/+12
ast27x0: Show build date and git version
2025-04-25ast27x0: Show build date and git versionJamin Lin2-4/+12
Add print_build_info() to display build date, time, and GIT_VERSION. GIT_VERSION is passed via Makefile using git-<commit> format. Build date and time are injected via __DATE__ and __TIME__ macros. ``` Build Date : Apr 25 2025 02:11:30 FW Version : git-82bed5c ``` Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2025-04-23Merge pull request #5 from jamin-aspeed/ast27x0Hao Wu33-3/+8181
Add initial support for AST27x0
2025-04-21Add initial support for AST27x0Jamin Lin33-3/+8181
- start.S and bootrom.ld The SRAM size is 128KB, with a start address of 0x10000000. Create a global variable "next_boot_addr" to store the BL31 load address (Trusted Firmware-A). When CPU0 calls the "load_boot_image" function, the function will return the BL31 address, which will be placed in the X0 register. This address is then assigned to "next_boot_addr" as the BL31 address, and an event is sent to notify CPU1, CPU2, and CPU3. Afterward, CPU0 jumps to the BL31 address. Meanwhile, CPU1, CPU2, and CPU3 continuously check if "next_boot_addr" is non-zero. Once it is set, they also jump to the BL31 address. - lib/libfdt To parse the U-Boot FIT image, use the library from the DTC repository: https://github.com/dgibson/dtc. - lib/libc/minimal To build "libfdt/fdt.c" and "libfdt/fdt_ro.c", support for API functions like "strlen" and "memcpy" is required. These functions are provided by "string.c", which can be found in the Zephyr repository: https://github.com/zephyrproject-rtos/zephyr/tree/main/lib/libc/minimal. - uart_aspeed.c To develop vBootROM, add this driver to support the serial console. This allows users to view logs from the console for debugging purposes. This file is based on the driver located at: https://github.com/AspeedTech-BMC/zephyr/blob/aspeed-main-v3.7.0/drivers/serial/uart_aspeed.c. It only support TX. - uart_console.c` I created a "uprintf" function, which is very similar to the "printf" function, for development purposes to display UART logs on the console. - image.c This is the main function of vBootROM for AST27x0. It initializes the UART and registers the console callback function. Next, it searches for the U-Boot FIT image within the address range of 0x100000000 to 0x100400000. If the U-Boot FIT image is found, it parses all sub-images in the "/images" node to retrieve their data and load addresses. The data is then copied to their respective load addresses. Finally, it returns the BL31 address as the next boot jump address. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2025-02-19Merge pull request #3 from haowu4682/devHavard Skinnemoen1-10/+27
Dev
2023-08-18Dynamically detects NPCM8XX UBOOT destination and size.Hao Wu1-10/+10
2022-09-29Automatically search for UBOOT location for NPCM8xx images.Hao Wu1-9/+26
2022-03-31Merge pull request #2 from haowu4682/masterHavard Skinnemoen11-41/+420
Add basic NPCM8XX support
2022-03-23Add a simple README file to describe each subdirHao Wu1-0/+10
2022-03-01Add NPCM8XX simple bootromHao Wu5-0/+369
2022-03-01Move NPCM7XX bootrom to a subdirectoryHao Wu5-0/+0
2020-06-24Merge pull request #1 from google/disable-build-idHavard Skinnemoen1-1/+1
Fix build with gcc-9 arm-linux-gnueabi toolchain
2020-06-24Fix build with gcc-9 arm-linux-gnueabi toolchainHavard Skinnemoen1-1/+1
Linux toolchains link dynamically by default, so pass -static. gcc also adds a .note.gnu.build-id to the beginning of the file, which messes up our reset vector when converting to a raw binary file. Passing --build-id=none to the linker gets rid of it. Change-Id: If64eb0fe7298480d5a9c04730088d74b32bcb082
2020-06-09Super simple boot ROM for npcm7xxHavard Skinnemoen8-0/+674
This is able to parse the boot block header, copy it into SRAM and jump to it. Secure booting or anything vaguely advanced is not supported. Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Change-Id: I88b567e8dba25cd75a3f37824698bcbefc89a98f