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<section id="skiboot-5-9-6">
<span id="id1"></span><h1>skiboot-5.9.6<a class="headerlink" href="#skiboot-5-9-6" title="Permalink to this headline">¶</a></h1>
<p>skiboot 5.9.6 was released on Friday December 15th, 2017. It replaces
<a class="reference internal" href="skiboot-5.9.5.html#skiboot-5-9-5"><span class="std std-ref">skiboot-5.9.5</span></a> as the current stable release in the 5.9.x series.</p>
<p>Over <a class="reference internal" href="skiboot-5.9.5.html#skiboot-5-9-5"><span class="std std-ref">skiboot-5.9.5</span></a>, we have a few bug fixes, they are:</p>
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<li><p>sensors: occ: Skip counter type of sensors</p>
<p>Don’t add counter type of sensors to device-tree as they don’t
fit into hwmon sensor interface.</p>
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<li><p>p9_stop_api updates to support IMC across deep stop states.</p></li>
<li><p>opal/xscom: Add recovery for lost core wakeup scom failures.</p>
<p>Due to a hardware issue where core responding to scom was delayed due to
thread reconfiguration, leaves the SCOM logic in a state where the
subsequent scom to that core can get errors. This is affected for Core
PC scom registers in the range of 20010A80-20010ABF</p>
<p>The solution is if a xscom timeout occurs to one of Core PC scom registers
in the range of 20010A80-20010ABF, a clearing scom write is done to
0x20010800 with data of ‘0x00000000’ which will also get a timeout but
clears the scom logic errors. After the clearing write is done the original
scom operation can be retried.</p>
<p>The scom timeout is reported as status 0x4 (Invalid address) in HMER[21-23].</p>
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