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2019-12-16opal-msg: endian fixes for opal-msg.c and opal_queue_msg callersNicholas Piggin9-15/+30
Reported-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16opal-api: add endian conversions to most opal callsNicholas Piggin13-74/+125
This adds missing endian conversions to most calls, sufficient at least to handle calls from a kernel booting on mambo. Subsystems requiring more extensive changes (e.g., xive) will be done with individual changes. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16cpu: use dt accessor device tree accessNicholas Piggin6-17/+15
In several cases the make test reference .dts files were incorrectly byteswapped, these are fixed here too. Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16capp: fix endian conversionNicholas Piggin1-1/+1
Acked-by: Stewart Smith <stewart@flamingspork.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-06xscom: Don't log xscom errors caused by OPAL callsOliver O'Halloran1-4/+11
The XSCOM read/write OPAL calls are largely there to support running PRD in the OS. PRD itself handles submitting error logs (if needed) when a XSCOM operation fails so there's no need to send an error log from inside of OPAL. Cc: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-04hw/p8-i2c: Clean up interrupt maskingOliver O'Halloran1-10/+25
There's three interrupt registers defined for the I2C master: 1. Interrupt mask 2. Raw interrupt condition bits 3. Masked interrupt condition bits All the I2C master interrupts are LSIs so the raw condition bits will only go to zero if the interrupt condition is dealt with. As a result the latter two registers are read only. For writes their addresses are re-used as atomic OR and atomic AND update registers for the mask register. When unmasking interrupts we currently do that via the atomic OR register and mask via the atomic AND, but we use the interrupt condition register macro names. This is a bit confusing and the documentation isn't super clear about the behaviour so fix the macro names in favour of something saner. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-04hw/p8-i2c: Don't print warnings when dumping registersOliver O'Halloran1-42/+10
There's not much point complaining if we can't collect debug data. Log a obviously-wrong value and continue. Also convert to using i2cm_read_reg() rather than xscom_read() directly while we're here. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-04phb4: Add PHB options get/set OPAL callsAlexey Kardashevskiy1-0/+59
These are new OPAL calls to tweak various PHB parameters. The first two are: - TVT Select 'GTE4GB' Option of the PHB control register to enable use of the second TVE for DMA trafic just above 4GB; - MMIO EEH Disable to disable EEH for all MMIO commands. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-04npu2: Clear fence on all bricksAlexey Kardashevskiy1-5/+12
A bug in the NVidia driver can cause an UR HMI which fences bricks (links). At the moment we clear fence status only for bricks of a specific devices, however this does not appear to be enough and we need to clear fences for all bricks. This is ok as we do not allow using GPUs individually anyway. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-27FSP/IPMI: Handle FSP reset reloadVasant Hegde1-0/+34
FSP IPMI driver serializes ipmi messages. It sends message to FSP and waits for response before sending new message. It works fine as long as we get response from FSP on time. If we have inflight ipmi message during FSP R/R, we will not get resonse from FSP. So if we initiate inband FSP R/R then all subsequent inband ipmi message gets blocked. Sequence: - ipmitool mc reset cold - <FSP R/R complete> - ipmitool <any command> <-- gets blocked This patch clears inflight ipmi messages after FSP R/R complete. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Cc: skiboot-stable@lists.ozlabs.org Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-19npu2/hw-procedures: Remove assertion from check_credits()Reza Arbab1-9/+6
The RX clock mux in the NVLink PHY can glitch, which will manifest in hard to diagnose behavior--at best, a checkstop during the first link traffic. The only reliable way we found to detect this was by checking for a discrepancy in the credits we expect to receive during link training. Since the time the check was added, we've found that * Commit ac6f1599ff33 ("npu2: hw-procedures: Add phy_rx_clock_sel()") does work around the original glitch. * Asserting is too harsh. Before root cause was established, it was thought this could have been a manufacturing defect and we wanted to loudly fail hardware acceptance boot cycle tests. * It seems there is a valid situation in which credits are off from the expected value. During GPU hot reset, a CPU prefetch across the link can affect the credit count before we check. Given all of the above, remove the assert(). Cc: stable # 6.0.x Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-14hw/test: Make tests quieterOliver O'Halloran1-2/+2
The physmap tests prints a few hundred lines of: Assigning BAR [8] type:01 index:0 0x0000200000000000 for 0x0000034000000000 Assigning BAR [8] type:02 index:5 0x0000234000000000 for 0x0000002000000000 Make it not do that. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-14IPMI: Trigger OPAL TI in abort path.Mahesh Salgaonkar1-7/+23
The current assert/abort implementation for BMC based system invokes cec reboot after printing backtrace. This means that BMC never gets notified about OPAL crash/termination. This sometimes leads into never ending IPL-ing loop if OPAL keeps aborting very early in boot path. Trigger a software xstop (OPAL TI) to inform BMC about the OPAL termination. BMC is capable of catching checkstop signal and facilitate in rebooting (IPL-ing) host. With AutoReboot policy, OpenBMC handles checkstop signals and counts them against the reboot counter. In cases where OPAL is crashing before host reaches to runtime, OpenBMC will move the system in Quiesced state after 3 or so attempts of IPL/reboot so that system can be debugged. When OPAL triggers software checkstop it causes all the CPU threads to be stooped and moved to quiesced state. Hence OPAL don't need to explicitly stop all CPUs before calling software xstop. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11Remove dead POWER7 codeNicholas Piggin14-118/+28
There are a number of proc_gen branches removed that are trivially dead code and comments that refer to P7. As well as those: - Oliver points out that add_xics_icps() must be unused on POWER8 because it asserts if number of threads > 4, so remove it. - Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all references to opal_boot_trampoline, so remove that. - It also removed the only non-trival choose_bus implementation, so that is removed and its caller simplified. - Remove the paca code, later CPUs use pcia. Cc: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11psi: update registers to reflect >= P8 PHBSCRNicholas Piggin1-13/+3
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11xive/p9: sbe size debug print fixNicholas Piggin1-1/+1
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11xive/p9: use predefined bitmasks to manipulate EQ addressesNicholas Piggin1-2/+3
This catches one more case missed by commit 2354857fca. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11xive/p9: improve cache watch type checkingNicholas Piggin1-46/+40
The cache update functions take void * pointer with sizing information in order to operate on some fundamentally different types. Make specific functions for each type, which use proper types. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11build: fix non-constant build assertsNicholas Piggin1-6/+1
BUILD_ASSERT can not be used for constants generated by the assembler or linker. This results in variable length arrays that do not catch the failure condition. This was caught by sparse. Remove these and add some equivalent as/ld checks which actually do the right thing. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11slw: slw_reinit fix array overrunNicholas Piggin1-1/+1
The slw patch saving array is too small, which results in slw_reinit overwriting 32 bytes beyond the end of it. The size is increased to 0x100, which is the architecture interrupt vector size. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-07prd: Fix FSP - HBRT firmware_notify messageVasant Hegde1-4/+8
Commit eb86b148 added FSP -> HBRT notify message support. I assumed that we just need to construct `firmware notify` PRD message and pass it to HBRT. But HBRT expects OPAL to pass `struct prd_fw_msg` message with message type PRD_FW_MSG_TYPE_HBRT_FSP. Fixes: eb86b148 (prd: Implement generic FSP - HBRT interface) Cc: Daniel M. Crowell <dcrowell@us.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-05prd: Fix prd message queuing interfaceVasant Hegde1-26/+20
OPAL_MSG_PRD interface can handle message size <= OPAL_MSG_FIXED_PARAMS_SIZE. But kernel prd driver had a bug where it will not copy partial data to user space. This will create problem as opal-prd daemon tries to read message continuously. Commit 9cae036fa fixed this issue by enhancing opal-prd to allocate bigger message size based on device tree. For backward compatability (new OPAL and old kernel/userspace) lets restrict OPAL_MSG_PRD messaging interface to send upto 32 bytes data. This is fine as most of the messages are less than 32 bytes except FSP - HBRT messages ...which is new feature. Cc: Jeremy Kerr <jk@ozlabs.org> Cc: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-05prd: Improve debug logsVasant Hegde1-1/+2
.. helps in debugging. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-05npu2-opencapi: Fix integer promotion bug in LPC allocationAndrew Donnellan1-1/+1
If you try to allocate an amount of LPC memory that's not a power of 2, we round the value up to the nearest power of 2. By the magic of C, "1 << n" gets treated as an int, even if you're assigning it to a uint64_t. Change 1 to 1ULL to fix this. (C, it's great.) Reported-by: Alastair D'Silva <alistair@d-silva.org> Cc: skiboot-stable@lists.ozlabs.org Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-05VAS: Alloc IRQ and port address for each VAS instanceHaren Myneni1-0/+37
Setup IRQ and trigger port for each VAS instance. Export these values through device-tree with 'interrupts' and 'ibm,vas-port' properties in each VAS device node. Kernel setup IRQ and register port address for each send window. Enable 'vas-user-space' NVRAM config to allocate IRQ sources and provide 'interrupts' property. nvram -p ibm,skiboot --update-config vas-user-space=enable Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04hw/port80: Squash No SYNC errorOliver O'Halloran2-4/+10
On Aspeed BMCs can be configured to route LPC IO address 0x80 to a GPIO port. Some systems use this to implement a boot progress indicator, but not all of them. There's no easy way to tell if this has been setup or not and if it hasn't we get an LPC SYNC no-response error from out LPC master. When we reach Linux and enable interrupts this results in this spurious error being printed: LPC[000]: Got SYNC no-response error. Error address reg: 0xd0010082 lpc_probe_write() is intended to catch situations where the peripherial being written to might not be configured, so use that instead of lpc_outb() to squash the error. Cc: Ranga <stewart@flamingspork.com> Cc: Andrew Jeffery <andrew@aj.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au> [oliver: fixed the test] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce the ESB magic MMIO offsetsCédric Le Goater1-10/+10
The following offsets into the ESB MMIO allow to read or manipulate the PQ bits. They must be used with an 8-byte load instruction. They all return the previous state of the interrupt (atomically). Additionally, some ESB pages support doing an EOI via a store and some ESBs support doing a trigger via a separate trigger page. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: use predefined bitmasks to manipulate EQ addressesCédric Le Goater1-3/+3
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove XIVE_INT_SAFETY_GAPCédric Le Goater1-5/+9
It was used by bringup code only. Using HW interrupt numbers in a high range was a way to check that HW interrupt numbers (OPAL) and logical interrupt numbers (Linux) were not getting mixed in the event queues. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce NVT_SHIFTCédric Le Goater1-2/+5
This defines the size of our VP space which is constrained by the definition of the END structure in the XIVE architecture for POWER9: #define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) #define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) The NVT/VP id is returned to the hypervisor by the OPAL call opal_xive_get_vp_info() and later pushed in W2 of the OS CAM line when a vCPU is dispatched on an HW thread. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove ACK# setting in the NVTCédric Le Goater1-1/+0
The pressure relief is disabled (PC_TCTXT_CFG_STORE_ACK) because we use the same field in the NVT W1 to stash the VP END base index. We do not need to disable manually the ACK# register in the NVT W5. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: cleanup all EQs when a VP block is freed.Cédric Le Goater1-1/+1
EQ 7 was missing from the cleanup loop. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: fix silent escalation EQ setupCédric Le Goater1-1/+3
When setting the silent/gather escalation for a VP, all EQs [0-6] should point to the silent EQ 7. Fix the loop in routine xive_setup_silent_gather() to include EQ 6 which was missing. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce definitions for prioritiesCédric Le Goater1-8/+16
The priority number 7 is used in a couple of places but it has different meanings. It can be the maximum priority number or the escalation priority number. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: fix EQ bitmap assignment when allocation failsCédric Le Goater1-6/+7
Wehn allocating a EQ set for a VP, the EQ base index bit is marked as allocated even if allocation fails, due to a lack of available pages. Move bit assignment at the end of xive_alloc_eq_set(). Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: obsolete OPAL_XIVE_IRQ_SHIFT_BUG flagsCédric Le Goater2-7/+1
These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0 processors. HW395455 P9/PHB4: Wrong Interrupt ESB CI Load Opcode Location in 64K page mode Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: obsolete OPAL_XIVE_IRQ_*_VIA_FW flagsCédric Le Goater1-12/+0
These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0 processors. Keep the flags in case of a similar issue in the next generation of the XIVE logic and keep it also for Linux which still has handlers in its XIVE layer. However, there is no need to keep the code in POWER9 XIVE driver. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove dead codeCédric Le Goater1-4/+0
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove code not using block group modeCédric Le Goater1-208/+1
block group mode is now required, it can not be disabled. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove code not using indirect modeCédric Le Goater1-111/+12
An indirect table is a one page array of XIVE VSDs pointing to subpages containing XIVE virtual structures: NVTs, ENDs, EASs or ESBs. The OPAL XIVE driver uses direct tables for the EAS and ESB tables. The number of interrupts being 1M, the tables are respectivelly 256K and 8M per chip. We want the EAS lookup to be fast so we keep this table direct. The NVT and END are bigger structures (64 and 32 bytes). If the table were direct, we would use 32M and 32M of OPAL memory per chip. They are indirect today and Linux allocates the pages on behalf of OPAL when a new indirect subpage is needed. We plan to increase the NVT space and END space in P10. Remove USE_INDIRECT ifdef and associated code not used anymore. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: use MMIO access for VC_EQC_CONFIGCédric Le Goater1-1/+1
There is no reason to issue loads on XSCOM when syncing the interrupt controller. All should be in place to use MMIOs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: minor cleanup of the interfaceCédric Le Goater2-2/+3
The XIVE driver exposes an API to the core OPAL layer and to other OPAL drivers. This is a minor cleanup preparing ground for future XIVE logic. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce header files for the registersCédric Le Goater1-2/+4
This is moving the definitions of the registers of the P9 XIVE interrupt controller and the P9 XIVE internal structures in a specific header file and moving the definitions related to the thread interrupt context area to a common file. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04npu3: Make SALT CMD_REG writableReza Arbab1-3/+4
CMD_REG should be writable, not read-only. Fix this, initializing it with a default "unset" value (0xffffffff). Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04npu3: Improve SALT log outputReza Arbab1-3/+5
Add a log line for when the PPE indicates it's not in the ready state, and make all the SALT lines start with a capital to look nicer. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04npu3: Add ibm, ioda2-npu3-phb to compatible propertyReza Arbab1-2/+7
Though they are currently identical to the OS, it may become necessary to distinguish npu3 phbs from npu2 ones at some point. Add a unique string to the compatible property. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22occ-sensor: clean dt properties if sensor is not availableBalamuruhan S1-0/+4
In `occ_sensor_init()` device tree node is created for sensor-goups and performs `occ_sensor_sanity()` check to initialize the device tree. But if there are no sensors like in Qemu, sanity check fails but still device tree populates the sensor-groups node wrongly as the node created is not cleaned up. Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Log a warning when resetting a broken deviceFrederic Barrat1-0/+4
On P9, the NPU doesn't support recovery if the link goes down unexpectedly. It was not fully verified. We mark the device as broken when we receive an error interrupt from the NPU. However, there's nothing to prevent the OS from trying to reset the device; It may or may not work, it's unsupported territory, so let's log a message to make it clear, as it could help when debugging. We haven't hit any cases where the reset goes badly enough that we'd want to prevent it, so let it go for now. We can revisit later if we have evidence that it's causing more problems than it is worth. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Handle OPAL_UNMAP_PE operation on set_pe() callbackFrederic Barrat1-1/+6
In a hot-unplug scenario, the OS will try to unmap the PE. Skiboot doesn't do anything with the linux PE for opencapi other than being a mailbox, but at least let's be consistent. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Activate PCI hotplug on opencapi slotFrederic Barrat1-4/+65
Implement the get_power_state() and set_power_state() callbacks for the opencapi slot and add properties in the device tree to mark the opencapi slot as hot-pluggable. We don't really power off/on the opencapi adapter. The slot at play here is the virtual slot associated to the virtual opencapi PHB. The real PCIe slot where the card is drawing its power from is untouched (skiboot is not even aware which PCIe slot the card is seated on). So the 'fake' power off is fencing the card and set it in reset so that the FPGA image can be updated. The 'fake' power on is not doing much, as the unfencing happens on the subsequent link training. Opencapi slots are named 'OPENCAPI-xxxx' where xxxx is the opal ID of the PHB/slot. This is meant to easily identify the slot used by an AFU device, as the AFU device names are also built around that ID. For example, the device /dev/ocxl/AFP3.0006:00:00.1.0 uses the slot OPENCAPI-0006. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
generated by cgit v1.1 at 2025-09-19 01:40:47 +0000