aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Expand)AuthorFilesLines
2021-06-24phb4: Avoid MMIO load freeze escalation on every chipMahesh Salgaonkar1-1/+5
2021-06-24phb4: Disable TCE cache line bufferFrederic Barrat1-0/+1
2021-06-24hw/imc: Disable only nest_imc devices if pause_microcode() failsMadhavan Srinivasan1-2/+16
2021-06-24Fix lock error when BT IRQ preempt BT timerlixg1-3/+5
2021-01-06SBE: Account cancelled timer requestVasant Hegde1-0/+3
2021-01-06SBE: Rate limit timer requestsVasant Hegde1-0/+22
2021-01-06SBE: Check timer state before scheduling timerVasant Hegde1-2/+4
2021-01-06Revert "mowgli: Limit slot1 to Gen3 by default"LuluTHSu1-20/+0
2021-01-06xscom: Fix xscom error logging caused due to xscom OPAL callGautham R. Shenoy1-2/+19
2021-01-06xive/p9: Remove assert from xive_eq_for_target()Cédric Le Goater1-1/+1
2020-11-02phb4: Finish removing P9 DD1 workaround on LSIsCédric Le Goater1-4/+1
2020-11-02mowgli: Limit slot1 to Gen3 by defaultLuluTHSu1-0/+21
2020-10-21FSP/NVRAM: Do not assert in vNVRAM statistics callVasant Hegde1-2/+1
2020-08-28fsp/dump: Handle non-MPIPL scenarioVasant Hegde1-4/+4
2020-08-28hw/phb4: Verify AER support before initialising AER regsOliver O'Halloran1-0/+3
2020-08-28hw/phb4: Actually enable error reportingOliver O'Halloran1-0/+1
2020-08-07imc: Use pir_to_core_id() rather than cpu_get_core_index()Benjamin Herrenschmidt1-4/+4
2020-08-07slw: Limit fused cores P9 to STOP0/1/2Benjamin Herrenschmidt1-1/+81
2020-08-07xive: Set the fused core mode properlyBenjamin Herrenschmidt1-0/+4
2020-08-07Add basic P9 fused core supportRyan Grimm1-1/+1
2020-08-07xive/p9: Enforce thread enablement before TIMA accessesCédric Le Goater1-0/+15
2020-08-07xive: Fix typos in commentsGustavo Romero1-2/+2
2020-08-07hw/psi-p9: Configure IRQ offset before XIVE notifyOliver O'Halloran1-10/+10
2020-07-02fsp: Skip sysdump retrieval only in MPIPL bootVasant Hegde1-3/+11
2020-06-30xive: Fix two typos in commentsGustavo Romero1-2/+2
2020-06-30prd: Do not assert if HBRT makes unsupported callVasant Hegde1-13/+29
2020-06-30mpipl: Move opal_mpipl_save_crashing_pir() call to platform specific codeVasant Hegde2-0/+7
2020-06-30mpipl: Delay MPIPL registration until OPAL init is completeVasant Hegde1-1/+1
2020-06-30uart: Actually swallow data if LPC is not workingVasant Hegde1-1/+1
2020-06-30dt: Set new property length in dt_resize_property()Thiago Jung Bauermann3-3/+0
2020-06-30xive/P9: Use NUM_INT_PRIORITIES in xive_reset()Cédric Le Goater1-1/+1
2020-06-30xive/p9: Introduce XIVE_ESB_SIZECédric Le Goater1-7/+8
2020-06-30xive/p9: use PAGE_SIZECédric Le Goater1-19/+19
2020-06-30hw/xive: Use XIVE_VSD_SIZE moreOliver O'Halloran1-2/+2
2020-06-30xive/p9: Introduce definitions for VP ids of HW threadsCédric Le Goater1-13/+22
2020-06-30xive/p9: Modify the size of the VP spaceCédric Le Goater1-8/+12
2020-06-30xive/p9: Force 64K page size on the IC and TM BARsCédric Le Goater1-21/+6
2020-06-30xive/p9: Clarify indirect table allocationCédric Le Goater1-12/+17
2020-06-30xive/p9: Use sizeof() instead of hardcoded valuesCédric Le Goater1-2/+3
2020-06-30xive/p9: Introduce XIVE_EQ_SHIFTCédric Le Goater1-2/+3
2020-06-30xive/p9: Clarify the escalation IRQ encodingCédric Le Goater1-4/+9
2020-06-30xive/p9: Introduce XIVE_EQ_ORDERCédric Le Goater1-8/+9
2020-06-30xive/p9: Introduce XIVE_ESB_SHIFTCédric Le Goater1-4/+6
2020-06-30xive/p9: Clarify the global IRQ number encodingCédric Le Goater1-6/+13
2020-06-30xive/p9: Introduce XIVE_INT_ORDERCédric Le Goater1-14/+20
2020-06-17test: Do gcov builds as a seperate passOliver O'Halloran1-1/+1
2020-06-11io: endian annotations and fixNicholas Piggin1-6/+6
2020-06-03xive: Fix typo and spelling in a commentGustavo Romero1-1/+1
2020-06-03occ: Fix false negatives in wait_for_all_occ_init()Gautham R. Shenoy1-30/+147
2020-06-03hw/phb4: Enable error interruptsOliver O'Halloran1-1/+39
generated by cgit v1.1 at 2024-07-16 21:03:57 +0000