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This patch adds the generic i2c driver infrastructure to handle multiple i2c
master cores present in the system and exposes structures and interfaces for
the client to perform I/O on the i2c slave devices.
The driver adds the capability to queue multiple requests from client and
let clients notified asynchronously after completion. It does that by
handling the i2c interrupt or through OPAL poller in the absence of
interrupt.
Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This makes OPAL use the OCC interrupt facility to send itself an interrupt
whenever the OPAL event bit is set as a result of an OPAL call that wasn't
itself opal_handle_interrupt() or opal_handle_hmi() (both of which we know
the OS will already deal with appropriately).
This ensures that OPAL event changes are notified to Linux via its
interrupt path which is necessary for it to properly broadcast the state
change to its various clients.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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After sending the FSP reset sequence via PSIHBCR, drive the PSI link down
without actually waiting for the PSI interrupt indicating the
'Link Inactive Transition'.
There have been cases where this interrupt doesn't arrive and we are left
high and dry waiting for it, while the FSP comes back up and thinks Sapphire
is not initializing the new link (bz 117526 for instance).
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The FPGA used on some open power machines generates regular pulses instead
of levels. In that case, reading the status might fail since it's not
latched. In that case, also check the latched event bit in the XIVR.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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This patch will fix the flow of triggering actual reset of the FSP.
Host should follow the following steps to reset FSP.
1.) Reading the HBC register
2.) Turning on bit 6 and writing the register (fsp reset)
3.) reading the register back
4.) clearing bit 6 and writing the register (clear fsp reset)
Test results:
Initiate HIR on FSP with the following commands
1) fsptelinit --disablerecovery
2) putmemproc 300000f8 0x00000000deadbeef
Sapphire traces:
SURV: Heartbeat Acknowledgment error from FSP
ELOG: Notified of log 0x50294535 (size: 6356)
FSPLED: FSP_CMD_SET_LED_STATE command received
ELOG: Notified of log 0x50294566 (size: 2708)
FSPLED: FSP_CMD_GET_LED_STATE command received
FSPLED: FSP_CMD_SET_LED_STATE command received
ELOG: Notified of log 0x50294629 (size: 2744)
SURV: [ 9be1a4cc2e] Surv ACK timed out; initiating R/R
FSP: fsp_trigger_reset() entry
FSP: Writing reset to DRCR
FSP: DRCR changed, old = 0, new = 8100
SURV: [ 9c1f97eccd] Sending the hearbeat command to FSP
FSP: DRCR changed, old = 8100, new = 0
FSP: DRCR ack received. Triggering reset
PSI: Driving FSP reset via PSI
PSI[0x000]: FSP reset start PSIHBCR set to def0300000000000
PSI[0x000]: FSP reset complete. PSIHBCR set to dcf0300000000000
PSI[0x000]: PSI mgmnt interrupt CR=0xdcf09100c0000000
PSI: PSI Reported Error
PSI: PSI Link Inactive Transition
PSI: SEMR set to fff0fff00000
PSI[0x000]: Disabling link!
PSI: PSIHB_CR (error bits) set to 48f0110040000000
PSI: starting link polling
FSP #0: Link down, starting R&R
FSPCON: Closed consoles on account of FSP reset/reload
SURV: Disabling surveillance
FSP: Closing NVRAM on account of FSP Reset
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
...
....
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0x48f0100040000000
PSI[0x000]: Poll CR=0xccf0300000000000
PSI[0x000]: Found active link!
PSI: stopping link polling
FSP: Connected to FSP-A
FSP #0: DISR stat change = 0x00000029
FSP #0: DISR stat change = 0x00000201
FSP #0: Detected R&R complete, acking
FSP #0: DISR stat change = 0x00000001
FSP: FSP assuming new role
FSP: Unhandled message ce0900
FSP: SP says Reset/Reload complete
DUMP: FipS dump available. ID = 0x6a000036 [size: 36086215 bytes]
FSP: Reassociating HVSI console 1
FSP: Reassociating HVSI console 2
SURV: Querying FSP's surveillance status
FSP: Reopening NVRAM of FSP Reload complete
FSP NVRAM: Opening nvram...
MDST: Table updated.
FSPCON: Got HMC interface query
SURV: Received heartbeat acknowledge from FSP
FSP: FSP query capabilities
After reset, FSP reached runtime state.
$ smgr mfgState
runtime
On FSP, HIR resgister set to 1 and reset reload is zero.
$ registry -l smgr
smgr/rr_count_hostinitiated:
0001 [..]
smgr/rr_count_other:
0000 [..]
Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com>
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Currently, we drive the link down when doing a host initated reset.
We should ideally reset the FSP and let it bring the link down.
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Currently this is done in the FSP code...
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Remove some code duplication and correct sequence handling.
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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So my great attempt at avoiding all re-entencies fails due to HBRT... at
least until we have some kind of way to thread things, it will have to
re-enter so let's bite the bullet, make the poller list walking lockless
(we'll handle removal when we have to, ie, not yet) and slightly extend
the coverage of the PSI lock while at it. All the other pollers already
have their own locks anyway so we are actually removing some overhead.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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