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Move this out of the astbmc specific part into a generic helper. This
allows us to use it more commonly.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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astbmc has some code to handle devices that are behind a "slot" on a
riser card that can't be added to the static slot tables for a system.
We probably want to use this code outside the slot table handling so
move it somewhere generic and rework it so slot table specifics aren't
buried inside it.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In P9 we get information about the physical PCIe slot topology
through the HDAT. As a rule we never directly consume the HDAT
inside of Skiboot and we always parse and incorporate the data
from HDAT into the Skiboot device tree.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[stewart@linux.vnet.ibm.com: add (C) header]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We are going need pci_wait_crs() in the PHB4 code so make it global.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The mbox protocol explicitly states that an erase is not required
before a write. This means that issuing an erase from userspace,
through the mtd device, and back returns a successful operation
that does nothing. Unfortunately, this makes userspace tools unhappy.
Linux MTD devices support the MTD_NO_ERASE flag which conveys that
writes do not require erases on the underlying flash devices. We
should set this property on all of our
devices which do not require erases to be performed.
NOTE: This still requires a linux kernel component to set the
MTD_NO_ERASE flag from the device tree property.
Signed-off-by: William A. Kennington III <wak@google.com>
Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[stewart@linux.vnet.ibm.com: slightly reword commit msg based on Suraj's comments]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In P8, hostboot provides mini device tree. It contains /ibm,firmware-versions
node which has various firmware component version details.
In P9, OPAL is building device tree. This patch adds support to parse VERSION
section of PNOR and create "/ibm,firmware-versions" device tree node.
Sample output:
/sys/firmware/devicetree/base/ibm,firmware-versions # lsprop .
occ "6a00709"
skiboot "v5.7-rc1-p344fb62"
buildroot "2017.02.2-7-g23118ce"
capp-ucode "9c73e9f"
petitboot "v1.4.3-p98b6d83"
sbe "02021c6"
open-power "witherspoon-v1.17-128-gf1b53c7-dirty"
....
....
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com>
Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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There are two cases where sync_icache is not called immediately
after instructions are modified.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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__gcov_exit() was added in GCC 7.1
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In the world of unit tests all "RAM" is valid
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Shuts LeakSanitizer up
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We were reserving all of memory up to the heap, which is fine
*unless* the system libc chooses to allocate something in that
block of memory that we use, which means we have overlapping
regions and general pain.
This should fix failing unit tests on some systems (e.g. Debian)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Fixes the following LeakSanitizer errors:
=================================================================
==32426==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 56 byte(s) in 1 object(s) allocated from:
#0 0x7fd94a1fa850 in malloc (/lib64/libasan.so.4+0xde850)
#1 0x4014d4 in main core/test/run-time-utils.c:30
#2 0x7fd94904c509 in __libc_start_main (/lib64/libc.so.6+0x20509)
Direct leak of 8 byte(s) in 1 object(s) allocated from:
#0 0x7fd94a1fa850 in malloc (/lib64/libasan.so.4+0xde850)
#1 0x4014f0 in main core/test/run-time-utils.c:32
#2 0x7fd94904c509 in __libc_start_main (/lib64/libc.so.6+0x20509)
Direct leak of 4 byte(s) in 1 object(s) allocated from:
#0 0x7fd94a1fa850 in malloc (/lib64/libasan.so.4+0xde850)
#1 0x4014e2 in main core/test/run-time-utils.c:31
#2 0x7fd94904c509 in __libc_start_main (/lib64/libc.so.6+0x20509)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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It's hardware after all...
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This sets the FIR, FIR mask and FIR action registers according to VAS
workbook v1.20. It also renames them to make it clear what they are.
Without this any VAS error will checkstop the machine, rather than
potentially be recoverable.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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If there are no VAS nodes in the device tree we will still print this
misleading message.
Chips are already printed as they are inited.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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When a complete reset occurs, after the PHB recovers it propagates a
reset down the wire to every device. At the same time, skiboot talks to
every device in order to restore the state of devices to what they were
before the reset.
In some situations, such as devices that recovered slowly and/or were
behind a switch, skiboot attempted to access config space of the device
before the link was up and the device could respond.
Fix this by retrying CRS until the device responds correctly, and for
devices behind a switch, making sure the switch has its link up first.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Tested-by: Hari Bathini <hbathini@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Signed-off-by: Russell Currey <ruscur@russell.cc>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This can be checked from config space, but we will need to know this when
restoring the PCI topology, and it is not always safe to access config
space during this period.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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POWER9 DD2 added some new "enable" bits that must be set for VAS to
work. These bits were unused in DD1.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Acked-By: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Just print an error if a region failed to add - at least then there will
be a trace somewhere about the problem.
Fixes: CID 147251
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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A rework of where some of the xscom regs are for POWER9 has resulted in
a scope issue where the same line attempts to simultaneously reference a
variable by the same name in global and function scope.
Change the value read by xscom_read to *_val
Fixes: CID 147808
Fixes: bda5e0ea Fix scom addresses for power9 nx checkstop hmi handling.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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According to Coverity:
le16_to_cpu(elf64->e_shnum) is promoted in
`le16_to_cpu(elf64->e_shentsize) * le16_to_cpu(elf64->e_shnum)`
to type int (32 bits, signed), then sign-extended to type
unsigned long long (64 bits, unsigned).
If `le16_to_cpu(elf64->e_shentsize) * le16_to_cpu(elf64->e_shnum)`
is greater than 0x7FFFFFFF, the upper bits of the result will all be 1.
I'm sure in practice this can't happen since this would require
either/or e_shnum and e_shentsize to be quite large.
Fixes: CID 138019, 137707, 137706, 137708
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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P9 supports PCI peer-to-peer: a PCI device can write directly to the
mmio space of another PCI device. It completely by-passes the CPU.
It requires some configuration on the PHBs involved:
1. on the initiating side, the address for the read/write operation is
in the mmio space of the target, i.e. well outside the range normally
allowed. So we disable range-checking on the TVT entry in bypass mode.
2. on the target side, we need to explicitly enable p2p by setting a
bit in a configuration register. It has the side-effect of reserving
an outbound (as seen from the CPU) store queue for p2p. Therefore we
only enable p2p on the PHBs using it, as we don't want to waste the
resource if we don't have to.
P9 supports p2p mmio writes. Reads are currently only supported if the
two devices are under the same PHB but that is expected to change in
the future, and it raises questions about intermediate switches
configuration, so we report an error for the time being.
The patch adds a new OPAL call to allow the OS to declare a p2p
(initiator, target) pair.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Implement the function vas_get_wcbs_bar() that returns the Window
Context Backing store address register. NX driver uses this function
to initialize its UMAC Send WC register.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The nest accelerator (NX) will need this interface to initialize its
UMAC MMIO BAR.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Create a device tree node for VAS and add properties that Linux
will need to configure/use VAS.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Define helpers get_paste_bar() and get_paste_bitfield(), to facilitate
computing the the physical power bus "paste" address for any window on
a given chip. A follow-on patch will export these values to Linux via
the device tree.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Initialize the VAS registers on each of instance that we discover.
Initializing VAS involves writing either pre-defined values or allocated
addresses to appropriate SCOM addresses.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: update phys_map_get API usage]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Adds a generic API to clear sensor groups. OCC inband sensor groups
such as CSM, Profiler and Job Scheduler can be cleared using this API.
It will clear the min/max of all sensors belonging to OCC sensor
groups.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add support to parse and export OCC inband sensors which are copied
by OCC to main memory in P9. Each OCC writes three buffers which
includes one names buffer for sensor meta data and two buffers for
sensor readings. While OCC writes to one buffer the sensor values
can be read from the other buffer. The sensors are updated every
100ms.
This patch adds power, temperature, current and voltage sensors to
/ibm,opal/sensors device-tree node which can be exported by the
ibmpowernv-hwmon driver in Linux.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add support to set the CPU-GPU power shifting ratio which is used by
the OCC power capping algorithm. PSR value of 100 takes all power away
from CPU first and a PSR value of 0 caps GPU first.
Documentation enhanced by Stewart Smith.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds a generic powercap framework and exports OCC powercap
sensors using which system powercap can be set inband through OPAL-OCC
command-response interface.
Documentation for powercap enhanced by Stewart Smith.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Regions with the no-map property should be handled seperately to
"normal" firmware reservations. When creating mem_region regions
from a reserved-memory DT node use the no-map property to select
the right reservation type.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add a lock so that only one thread can print a backtrace at a time.
This should prevent multiple threads from garbaling each other's
backtraces.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Fast-reboot has a memory leak which causes the system to crash after about
250 fast-reboots. The patch fixes the memory leak.
The cause of the leak was the pci_device's being freed, without freeing
the pci_slot within it.
Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Fixes build warnings when running with higher optimization than -O0
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Today we have an issue where the NUMA nodes corresponding
to GPU's have the same affinity/distance as normal memory
nodes. Our reference-points today supports two levels
[0x4, 0x4] for normal systems and [0x4, 0x3] for Power8E
systems. This patch adds a new level [0x4, X, 0x2] and
uses node-id as at all levels for the GPU.
Cc: Reza Arbab <arbab@linux.vnet.ibm.com>
Cc: Alistair Popple <alistair@popple.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Reviewed-by: Alistair Popple <alistair@popple.id.au>
Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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PCI link training is responsible for a huge chunk of the skiboot boot
time, so add the ability to trace it waiting in the main state
machine.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Currently during boot there a long delay while we wait for the PHBs to
be reset and train. During this time, there is no output from skiboot
and the last message doesn't give an indication of what's happening.
This boosts the PHB reset message from info to notice so users can see
what's happening during this long period of waiting.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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At the moment, if we get passed flags we don't know about, we
return OPAL_UNSUPPORTED but we still perform whatever actions
was requied by the flags we do support. Additionally, on P8,
we attempt a SLW re-init which hasn't been supported since
Murano DD2.0 and will crash your system.
It's too late to fix on existing systems so Linux will have to
be careful at least on P8, but to avoid future issues let's clean
that up, make sure we only use slw_reinit() when HILE isn't
supported.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[stewart@linux.vnet.ibm.com: retain OPAL_UNSUPPORTED]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This can work around problems where Linux fails to properly
cleanup part or all of the TLB on kexec.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Scom addresses for NX status, DMA & ENGINE FIR and PBI FIR has changed
for Power9. Fixup thoes while handling nx checkstop for Power9.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Scom addresses for CORE FIR (Fault Isolation Register) and Malfunction
Alert Register has changed for Power9. Fixup those while handling core
checkstop for Power9.
Without this change HMI handler fails to check for correct reason for
core checkstop on Power9.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The only sensible thing to do if this fails is to abort() as we've
likely just failed reserving reserved memory regions, and nothing
good comes from that.
Found by static analysis
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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There's a bug in current Linux kernels leaving crap in those registers
accross kexec and not sanitizing them on boot. This breaks kexec under
some circumstances (such as booting a hash kernel from a radix one
on P9 DD2.0).
The long term fix is in Linux, but this workaround is a reasonable
way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus()
and shouldn't have adverse effects.
We could also use that same mechanism to cleanup other things as
well such as restoring some other SPRs to their default value in
the future.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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IMC (In Memory Collection) catalog is a repository of information
about the Performance Monitoring Units (PMUs) and their events under
the IMC infrastructure. The information include :
- The PMU names
- Event names
- Event description
- Event offsets
- Event scale
- Event unit
The catalog is provided as a flattened device tree (dtb). Processors
with different PVR values may have different PMU or event names. Hence,
for each processor, there can be multiple device tree binaries (dtbs)
containing the IMC information. Each of the dtb is compressed and forms
a sub-partition inside the PNOR partition "IMA_CATALOG". Here is a link
to the commit adding this partition to PNOR :
https://github.com/open-power/pnor/commit/c940142c6dc64dd176096dc648f433c889919e84
So, each compressed dtb forms a sub-partition inside the IMC pnor
partition and can be accessed/loaded through a sub-partition id which
is nothing but the PVR id. Based on the current processor's PVR, the
appropriate sub-partion will be loaded.
Note however, that the catalog information is in the form of a dtb and
the dtb is compressed too. So, the sub-partition loaded must be
decompressed first before we can actually use it.
It is important to mention here that while a PNOR image built for one
processor is specific to only that processor and isn't portable, a
single system generation (Processor version) may have multiple revisions
and these revisions may have some changes in their IMC PMUs and events,
and hence, the need for multiple IMC DTBs.
The sub-partition that we obtain from the IMC pnor partition is a
compressed device tree binary. We uncompress it using the libxz's
functions. After uncompressing it, we link the device tree binary to the
system's device tree. The kernel can now access the device tree and get
the IMC PMUs and their events' information.
Not all the IMC PMUs listed in the device tree may be available. This is
indicated by imc availability vector (which is a part of the IMC control
block structure). We need to check this vector and make sure to remove
the IMC device nodes which are unavailable.
Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com>
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: use pr_fmt, fix failure path for resource load]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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When there is a new device tree that needs to be added to
the main dt of the opal (ex, IMC catalog dtb loaded from
pnor partition), we need to check for the phandle values
in the new incoming device tree before attaching it.
Reason is that, incoming device tree could already have
phandle values initialized for its nodes. Now, if we attach
this new device tree to the main opal DT, we could
potentially hit phandle duplicate error (since the
phandles value usually start with 1).
To avoid this, a new helper function dt_adjust_subtree_phandle()
is added to scan the incoming device tree and update
node "phandle" accordingly based on the opal
"last_phandle" value.
Add to this, helper function also supports updates of
"properties" with in a node which may refer the
"phandle" value in the incoming device tree. Helper
function will also fix the "properties" field accordingly.
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add helper functions for "last_phandle" access/update and
modify functions to use helper functions.
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds new opal_reinit_cpus() flags to setup radix or hash
mode in HID[8] on POWER9.
By default HID[8] will be set. On P9 DD1.0, Linux will change
it as needed. On P9 DD2.0 hash works in radix mode (radix is
really "dual" mode) so KVM won't break and existing kernels
will work.
Newer kernels built for hash will call this to clear the HID bit
and thus get the full size of the TLB as an optimization.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Create a more generic helper for changing HID0 bits on all
processors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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