diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/chiptod.c | 3 | ||||
| -rw-r--r-- | hw/lpc.c | 27 | ||||
| -rw-r--r-- | hw/p8-i2c.c | 45 | ||||
| -rw-r--r-- | hw/xscom.c | 10 |
4 files changed, 30 insertions, 55 deletions
diff --git a/hw/chiptod.c b/hw/chiptod.c index 88bc466..49b84e7 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -42,8 +42,7 @@ /* -- TOD PIB Master reg -- */ #define TOD_PIB_MASTER 0x00040027 #define TOD_PIBM_ADDR_CFG_MCAST PPC_BIT(25) -#define TOD_PIBM_ADDR_CFG_SLADDR_MASK PPC_BITMASK(26,31) -#define TOD_PIBM_ADDR_CFG_SLADDR_LSH PPC_BITLSHIFT(31) +#define TOD_PIBM_ADDR_CFG_SLADDR PPC_BITMASK(26,31) /* -- TOD Error interrupt register -- */ #define TOD_ERROR 0x00040030 @@ -37,29 +37,22 @@ DEFINE_LOG_ENTRY(OPAL_RC_LPC_WRITE, OPAL_PLATFORM_ERR_EVT, OPAL_LPC, #define ECCB_DATA 3 /* b0023 -> b00218 */ #define ECCB_CTL_MAGIC 0xd000000000000000ul -#define ECCB_CTL_DATASZ_MASK PPC_BITMASK(4,7) -#define ECCB_CTL_DATASZ_LSH PPC_BITLSHIFT(7) +#define ECCB_CTL_DATASZ PPC_BITMASK(4,7) #define ECCB_CTL_READ PPC_BIT(15) -#define ECCB_CTL_ADDRLEN_MASK PPC_BITMASK(23,25) -#define ECCB_CTL_ADDRLEN_LSH PPC_BITLSHIFT(25) +#define ECCB_CTL_ADDRLEN PPC_BITMASK(23,25) #define ECCB_ADDRLEN_4B 0x4 -#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32,63) -#define ECCB_CTL_ADDR_LSH 0 +#define ECCB_CTL_ADDR PPC_BITMASK(32,63) -#define ECCB_STAT_PIB_ERR_MASK PPC_BITMASK(0,5) -#define ECCB_STAT_PIB_ERR_LSH PPC_BITLSHIFT(5) -#define ECCB_STAT_RD_DATA_MASK PPC_BITMASK(6,37) -#define ECCB_STAT_RD_DATA_LSH PPC_BITLSHIFT(37) +#define ECCB_STAT_PIB_ERR PPC_BITMASK(0,5) +#define ECCB_STAT_RD_DATA PPC_BITMASK(6,37) #define ECCB_STAT_BUSY PPC_BIT(44) -#define ECCB_STAT_ERRORS1_MASK PPC_BITMASK(45,51) -#define ECCB_STAT_ERRORS1_LSH PPC_BITLSHIFT(51) +#define ECCB_STAT_ERRORS1 PPC_BITMASK(45,51) #define ECCB_STAT_OP_DONE PPC_BIT(52) -#define ECCB_STAT_ERRORS2_MASK PPC_BITMASK(53,55) -#define ECCB_STAT_ERRORS3_LSH PPC_BITLSHIFT(55) +#define ECCB_STAT_ERRORS2 PPC_BITMASK(53,55) -#define ECCB_STAT_ERR_MASK (ECCB_STAT_PIB_ERR_MASK | \ - ECCB_STAT_ERRORS1_MASK | \ - ECCB_STAT_ERRORS2_MASK) +#define ECCB_STAT_ERR_MASK (ECCB_STAT_PIB_ERR | \ + ECCB_STAT_ERRORS1 | \ + ECCB_STAT_ERRORS2) #define ECCB_TIMEOUT 1000000 diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index f7074ad..47efafd 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -66,8 +66,7 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, /* I2C FIFO register */ #define I2C_FIFO_REG 0x4 -#define I2C_FIFO_MASK PPC_BITMASK(0, 7) -#define I2C_FIFO_LSH PPC_BITLSHIFT(7) +#define I2C_FIFO PPC_BITMASK(0, 7) /* I2C command register */ #define I2C_CMD_REG 0x5 @@ -75,19 +74,15 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_CMD_WITH_ADDR PPC_BIT(1) #define I2C_CMD_READ_CONT PPC_BIT(2) #define I2C_CMD_WITH_STOP PPC_BIT(3) -#define I2C_CMD_DEV_ADDR_MASK PPC_BITMASK(8, 14) -#define I2C_CMD_DEV_ADDR_LSH PPC_BITLSHIFT(14) +#define I2C_CMD_DEV_ADDR PPC_BITMASK(8, 14) #define I2C_CMD_READ_NOT_WRITE PPC_BIT(15) -#define I2C_CMD_LEN_BYTES_MASK PPC_BITMASK(16, 31) -#define I2C_CMD_LEN_BYTES_LSH PPC_BITLSHIFT(31) +#define I2C_CMD_LEN_BYTES PPC_BITMASK(16, 31) #define I2C_MAX_TFR_LEN 0xfff0ull /* I2C mode register */ #define I2C_MODE_REG 0x6 -#define I2C_MODE_BIT_RATE_DIV_MASK PPC_BITMASK(0, 15) -#define I2C_MODE_BIT_RATE_DIV_LSH PPC_BITLSHIFT(15) -#define I2C_MODE_PORT_NUM_MASK PPC_BITMASK(16, 21) -#define I2C_MODE_PORT_NUM_LSH PPC_BITLSHIFT(21) +#define I2C_MODE_BIT_RATE_DIV PPC_BITMASK(0, 15) +#define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21) #define I2C_MODE_ENHANCED PPC_BIT(28) #define I2C_MODE_DIAGNOSTIC PPC_BIT(29) #define I2C_MODE_PACING_ALLOW PPC_BIT(30) @@ -95,17 +90,14 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, /* I2C watermark register */ #define I2C_WATERMARK_REG 0x7 -#define I2C_WATERMARK_HIGH_MASK PPC_BITMASK(16, 19) -#define I2C_WATERMARK_HIGH_LSH PPC_BITLSHIFT(19) -#define I2C_WATERMARK_LOW_MASK PPC_BITMASK(24, 27) -#define I2C_WATERMARK_LOW_LSH PPC_BITLSHIFT(27) +#define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19) +#define I2C_WATERMARK_LOW PPC_BITMASK(24, 27) /* I2C interrupt mask, condition and interrupt registers */ #define I2C_INTR_MASK_REG 0x8 #define I2C_INTR_COND_REG 0x9 #define I2C_INTR_REG 0xa -#define I2C_INTR_ALL_MASK PPC_BITMASK(16, 31) -#define I2C_INTR_ALL_LSH PPC_BITLSHIFT(31) +#define I2C_INTR_ALL PPC_BITMASK(16, 31) #define I2C_INTR_INVALID_CMD PPC_BIT(16) #define I2C_INTR_LBUS_PARITY_ERR PPC_BIT(17) #define I2C_INTR_BKEND_OVERRUN_ERR PPC_BIT(18) @@ -135,16 +127,14 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_STAT_DATA_REQ PPC_BIT(6) #define I2C_STAT_CMD_COMP PPC_BIT(7) #define I2C_STAT_STOP_ERR PPC_BIT(8) -#define I2C_STAT_UPPER_THRS_MASK PPC_BITMASK(9, 15) -#define I2C_STAT_UPPER_THRS_LSH PPC_BITLSHIFT(15) +#define I2C_STAT_UPPER_THRS PPC_BITMASK(9, 15) #define I2C_STAT_ANY_I2C_INTR PPC_BIT(16) #define I2C_STAT_PORT_HISTORY_BUSY PPC_BIT(19) #define I2C_STAT_SCL_INPUT_LEVEL PPC_BIT(20) #define I2C_STAT_SDA_INPUT_LEVEL PPC_BIT(21) #define I2C_STAT_PORT_BUSY PPC_BIT(22) #define I2C_STAT_INTERFACE_BUSY PPC_BIT(23) -#define I2C_STAT_FIFO_ENTRY_COUNT_MASK PPC_BITMASK(24, 31) -#define I2C_STAT_FIFO_ENTRY_COUNT_LSH PPC_BITLSHIFT(31) +#define I2C_STAT_FIFO_ENTRY_COUNT PPC_BITMASK(24, 31) #define I2C_STAT_ANY_ERR (I2C_STAT_INVALID_CMD | I2C_STAT_LBUS_PARITY_ERR | \ I2C_STAT_BKEND_OVERRUN_ERR | \ @@ -153,10 +143,8 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, /* I2C extended status register */ #define I2C_EXTD_STAT_REG 0xc -#define I2C_EXTD_STAT_FIFO_SIZE_MASK PPC_BITMASK(0, 7) -#define I2C_EXTD_STAT_FIFO_SIZE_LSH PPC_BITLSHIFT(7) -#define I2C_EXTD_STAT_MSM_CURSTATE_MASK PPC_BITMASK(11, 15) -#define I2C_EXTD_STAT_MSM_CURSTATE_LSH PPC_BITLSHIFT(15) +#define I2C_EXTD_STAT_FIFO_SIZE PPC_BITMASK(0, 7) +#define I2C_EXTD_STAT_MSM_CURSTATE PPC_BITMASK(11, 15) #define I2C_EXTD_STAT_SCL_IN_SYNC PPC_BIT(16) #define I2C_EXTD_STAT_SDA_IN_SYNC PPC_BIT(17) #define I2C_EXTD_STAT_S_SCL PPC_BIT(18) @@ -167,15 +155,12 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_EXTD_STAT_LOW_WATER PPC_BIT(23) #define I2C_EXTD_STAT_I2C_BUSY PPC_BIT(24) #define I2C_EXTD_STAT_SELF_BUSY PPC_BIT(25) -#define I2C_EXTD_STAT_I2C_VERSION_MASK PPC_BITMASK(27, 31) -#define I2C_EXTD_STAT_I2C_VERSION_LSH PPC_BITLSHIFT(31) +#define I2C_EXTD_STAT_I2C_VERSION PPC_BITMASK(27, 31) /* I2C residual front end/back end length */ #define I2C_RESIDUAL_LEN_REG 0xd -#define I2C_RESIDUAL_FRONT_END_MASK PPC_BITMASK(0, 15) -#define I2C_RESIDUAL_FRONT_END_LSH PPC_BITLSHIFT(15) -#define I2C_RESIDUAL_BACK_END_MASK PPC_BITMASK(16, 31) -#define I2C_RESIDUAL_BACK_END_LSH PPC_BITLSHIFT(31) +#define I2C_RESIDUAL_FRONT_END PPC_BITMASK(0, 15) +#define I2C_RESIDUAL_BACK_END PPC_BITMASK(16, 31) /* Port busy register */ #define I2C_PORT_BUYS_REG 0xe @@ -30,15 +30,13 @@ SPR_HMER_XSCOM_STATUS_MASK)) #define XSCOM_ADDR_IND_FLAG PPC_BIT(0) -#define XSCOM_ADDR_IND_ADDR_MASK PPC_BITMASK(12,31) -#define XSCOM_ADDR_IND_ADDR_LSH PPC_BITLSHIFT(31) -#define XSCOM_ADDR_IND_DATA_MSK PPC_BITMASK(48,63) +#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(12,31) +#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63) #define XSCOM_DATA_IND_READ PPC_BIT(0) #define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) -#define XSCOM_DATA_IND_ERR_MASK PPC_BITMASK(33,35) -#define XSCOM_DATA_IND_ERR_LSH PPC_BITLSHIFT(35) -#define XSCOM_DATA_IND_DATA_MSK PPC_BITMASK(48,63) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) /* HB folks say: try 10 time for now */ #define XSCOM_IND_MAX_RETRIES 10 |