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author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-08-30 14:06:33 +0200 |
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committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-09-09 13:02:17 +0530 |
commit | 91650384becbeb320317f88721882ea55b4ede2f (patch) | |
tree | 5d3c05fe81d183c4c863e404a33097f8577d1c7b /platforms/astbmc | |
parent | 220b8861d375e8c620f2898411d00bcfe2ab9d4c (diff) | |
download | skiboot-91650384becbeb320317f88721882ea55b4ede2f.zip skiboot-91650384becbeb320317f88721882ea55b4ede2f.tar.gz skiboot-91650384becbeb320317f88721882ea55b4ede2f.tar.bz2 |
npu3: Remove GPU support on Swift
npu3 was only used on the Swift platform to add support for
GPUs (nvlink). The Swift platform has never left the lab and support
for GPUs on it is pretty much dead. So let's remove it.
The patch removes all related code. Device tree entries are no
longer created and in the very unlikely case that someone is still
trying to boot it, the linux nvlink discovery code should be quiet.
Tested by booting on Swift with no GPU.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'platforms/astbmc')
-rw-r--r-- | platforms/astbmc/swift.c | 89 |
1 files changed, 1 insertions, 88 deletions
diff --git a/platforms/astbmc/swift.c b/platforms/astbmc/swift.c index 991a79d..401aa6b 100644 --- a/platforms/astbmc/swift.c +++ b/platforms/astbmc/swift.c @@ -5,93 +5,8 @@ #include <skiboot.h> #include <ipmi.h> -#include <npu3.h> #include "astbmc.h" - -/* nvidia,link-speed uses a magic driver value */ -#define NVIDIA_LINK_SPEED_20000000000_BPS 3 -#define NVIDIA_LINK_SPEED_25781250000_BPS 8 -#define NVIDIA_LINK_SPEED_25000000000_BPS 9 - -static void swift_npu3_device_detect(struct npu3 *npu) -{ - struct npu3_dev *dev; - uint32_t node, gpu_index; - char slot[6]; - - node = P9_GCID2NODEID(npu->chip_id); - - switch (npu->index) { - case 0: - gpu_index = node * 2 + 1; - break; - case 2: - gpu_index = node * 2; - break; - default: - return; - } - - snprintf(slot, sizeof(slot), "GPU%d", gpu_index); - - npu3_for_each_dev(dev, npu) { - dev->type = NPU3_DEV_TYPE_NVLINK; - dt_add_property_string(dev->dn, "ibm,slot-label", slot); - dt_add_property_u64(dev->dn, "ibm,link-speed", 25000000000ull); - dt_add_property_cells(dev->dn, "nvidia,link-speed", - NVIDIA_LINK_SPEED_25000000000_BPS); - } -} - -#define SWIFT_POSSIBLE_GPUS 4 - -#define G(g) (devs[g] ? devs[g]->nvlink.gpu->dn->phandle : 0) -#define N(g) (devs[g] ? devs[g]->npu->nvlink.phb.dt_node->phandle : 0) - -#define add_peers_prop(g, p...) \ - if (devs[g]) \ - dt_add_property_cells(devs[g]->nvlink.gpu->dn, \ - "ibm,nvlink-peers", ##p) - -static void swift_finalise_dt(bool is_reboot) -{ - struct npu3 *npu; - struct npu3_dev *dev; - struct npu3_dev *devs[SWIFT_POSSIBLE_GPUS] = {}; - int32_t index; - - if (is_reboot) - return; - - /* Collect the first link we find for each GPU */ - npu3_for_each_nvlink_npu(npu) { - npu3_for_each_nvlink_dev(dev, npu) { - index = npu3_dev_gpu_index(dev); - if (index == -1 || index >= ARRAY_SIZE(devs)) - continue; - - if (dev->nvlink.gpu && !devs[index]) - devs[index] = dev; - } - } - - /* Add GPU interconnect properties */ - add_peers_prop(0, G(3), G(2), G(2), G(2), - G(3), G(1), G(1), G(1), - N(0), N(0), N(0), N(0)); - - add_peers_prop(1, G(2), G(3), G(3), G(3), - G(0), G(0), G(0), G(2), - N(1), N(1), N(1), N(1)); - - add_peers_prop(2, G(1), G(3), G(3), G(3), - G(0), G(0), G(0), G(1), - N(2), N(2), N(2), N(2)); - - add_peers_prop(3, G(2), G(2), G(2), G(0), - G(1), G(1), G(0), G(1), - N(3), N(3), N(3), N(3)); -} +#include <device.h> static bool swift_probe(void) { @@ -113,10 +28,8 @@ DECLARE_PLATFORM(swift) = { .cec_reboot = astbmc_ipmi_reboot, .elog_commit = ipmi_elog_commit, .exit = astbmc_exit, - .finalise_dt = swift_finalise_dt, .init = astbmc_init, .name = "Swift", - .npu3_device_detect = swift_npu3_device_detect, .pci_get_slot_info = dt_slot_get_slot_info, .probe = swift_probe, .resource_loaded = flash_resource_loaded, |