diff options
| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:56:55 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | ca9a2b8b315121c6c9d45ca98bc70c0bc8603beb (patch) | |
| tree | f5c319707950e5593e0287724b2273182e76fa12 /include | |
| parent | 882e867012a8c4af8a7bbd42b93816b2a2f3b827 (diff) | |
| download | skiboot-ca9a2b8b315121c6c9d45ca98bc70c0bc8603beb.zip skiboot-ca9a2b8b315121c6c9d45ca98bc70c0bc8603beb.tar.gz skiboot-ca9a2b8b315121c6c9d45ca98bc70c0bc8603beb.tar.bz2 | |
pau: enabling opencapi
Enable OpenCAPI mode for each brick which are connected to be used in
this mode. This is be done through 7 steps as described in the
P10 OCAPI 5.0 Processing Unit Workbook document, section:
17.1.3.1 Enabling OpenCAPI.
The following sequences must be performed:
1. Set Transport MUX controls to select OpenCAPI
2. Enable Clocks in XSL
3. Enable Clocks in MISC
4. Set NPCQ configuration
5. Enable XSL-XTS Interfaces
6. Enable State-machine allocation
Enabling the NTL/GENID BARS allows to access to the MMIO registers.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/pau-regs.h | 43 | ||||
| -rw-r--r-- | include/pau.h | 1 |
2 files changed, 44 insertions, 0 deletions
diff --git a/include/pau-regs.h b/include/pau-regs.h index 5779692..6aeb758 100644 --- a/include/pau-regs.h +++ b/include/pau-regs.h @@ -27,6 +27,10 @@ #define PAU_BLOCK_CQ_SM(n) PAU_BLOCK(4, (n)) #define PAU_BLOCK_CQ_CTL PAU_BLOCK(4, 4) +#define PAU_BLOCK_CQ_DAT PAU_BLOCK(4, 5) +#define PAU_BLOCK_XSL PAU_BLOCK(4, 0xE) +#define PAU_BLOCK_PAU_XTS PAU_BLOCK(7, 1) +#define PAU_BLOCK_PAU_MISC PAU_BLOCK(7, 2) /* * CQ_SM block registers @@ -37,21 +41,38 @@ #define PAU_MCP_MISC_CFG0 (PAU_BLOCK_CQ_SM(0) + 0x000) #define PAU_MCP_MISC_CFG0_MA_MCRESP_OPT_WRP PPC_BIT(9) #define PAU_MCP_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) +#define PAU_MCP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(44, 48) #define PAU_SNP_MISC_CFG0 (PAU_BLOCK_CQ_SM(0) + 0x180) #define PAU_SNP_MISC_CFG0_ENABLE_PBUS PPC_BIT(2) +#define PAU_SNP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(32, 36) +#define PAU_SNP_MISC_CFG0_OCAPI_C2 PPC_BITMASK(45, 49) #define PAU_NTL_BAR(brk) (PAU_BLOCK_CQ_SM(0) + 0x1b8 + (brk) * 8) +#define PAU_NTL_BAR_ENABLE PPC_BIT(0) #define PAU_NTL_BAR_ADDR PPC_BITMASK(3, 35) #define PAU_NTL_BAR_SIZE PPC_BITMASK(39, 43) #define PAU_MMIO_BAR (PAU_BLOCK_CQ_SM(0) + 0x1e0) #define PAU_MMIO_BAR_ENABLE PPC_BIT(0) #define PAU_MMIO_BAR_ADDR PPC_BITMASK(3, 27) #define PAU_GENID_BAR (PAU_BLOCK_CQ_SM(0) + 0x1e8) +#define PAU_GENID_BAR_ENABLE PPC_BIT(0) #define PAU_GENID_BAR_ADDR PPC_BITMASK(3, 32) +#define PAU_MISC_MACHINE_ALLOC (PAU_BLOCK_CQ_SM(0) + 0x268) +#define PAU_MISC_MACHINE_ALLOC_ENABLE PPC_BIT(0) /* CQ_CTL block registers */ +#define PAU_CTL_MISC_CFG2 (PAU_BLOCK_CQ_CTL + 0x010) +#define PAU_CTL_MISC_CFG2_OCAPI_MODE PPC_BITMASK(0, 4) +#define PAU_CTL_MISC_CFG2_OCAPI_4 PPC_BITMASK(10, 14) +#define PAU_CTL_MISC_CFG2_OCAPI_C2 PPC_BITMASK(15, 19) +#define PAU_CTL_MISC_CFG2_OCAPI_AMO PPC_BITMASK(20, 24) +#define PAU_CTL_MISC_CFG2_OCAPI_MEM_OS_BIT PPC_BITMASK(25, 29) +#define PAU_CTL_MISC_STATUS(brk) (PAU_BLOCK_CQ_CTL + 0x060 + (brk) * 8) +#define PAU_CTL_MISC_STATUS_AM_FENCED(brk) (PPC_BITMASK(41, 42) << ((brk)*32)) #define PAU_CTL_MISC_MMIOPA_CONFIG(brk) (PAU_BLOCK_CQ_CTL + 0x098 + (brk) * 8) #define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_ADDR PPC_BITMASK(1, 35) #define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_SIZE PPC_BITMASK(39, 43) +#define PAU_CTL_MISC_FENCE_CTRL(brk) (PAU_BLOCK_CQ_CTL + 0x108 + (brk) * 8) +#define PAU_CTL_MISC_FENCE_REQUEST PPC_BITMASK(0, 1) #define PAU_CTL_MISC_CFG_ADDR(brk) (PAU_BLOCK_CQ_CTL + 0x250 + (brk) * 8) #define PAU_CTL_MISC_CFG_ADDR_ENABLE PPC_BIT(0) #define PAU_CTL_MISC_CFG_ADDR_STATUS PPC_BITMASK(1, 3) @@ -61,4 +82,26 @@ #define PAU_CTL_MISC_CFG_ADDR_REGISTER_NBR PPC_BITMASK(20, 31) #define PAU_CTL_MISC_CFG_ADDR_TYPE PPC_BIT(32) +/* CQ_DAT block registers */ +#define PAU_DAT_MISC_CFG1 (PAU_BLOCK_CQ_DAT + 0x008) +#define PAU_DAT_MISC_CFG1_OCAPI_MODE PPC_BITMASK(40, 44) + +/* XSL block registers */ +#define PAU_XSL_WRAP_CFG (PAU_BLOCK_XSL + 0x100) +#define PAU_XSL_WRAP_CFG_CLOCK_ENABLE PPC_BIT(0) + +/* XTS block registers */ +#define PAU_XTS_CFG (PAU_BLOCK_PAU_XTS + 0x020) +#define PAU_XTS_CFG_OPENCAPI PPC_BIT(15) +#define PAU_XTS_CFG2 (PAU_BLOCK_PAU_XTS + 0x028) +#define PAU_XTS_CFG2_XSL2_ENA PPC_BIT(55) + +/* MISC block registers */ +#define PAU_MISC_OPTICAL_IO_CONFIG (PAU_BLOCK_PAU_MISC + 0x018) +#define PAU_MISC_OPTICAL_IO_CONFIG_OTL PPC_BITMASK(2, 3) +#define PAU_MISC_HOLD (PAU_BLOCK_PAU_MISC + 0x020) +#define PAU_MISC_HOLD_NDL_STALL PPC_BITMASK(0, 3) +#define PAU_MISC_CONFIG (PAU_BLOCK_PAU_MISC + 0x030) +#define PAU_MISC_CONFIG_OC_MODE PPC_BIT(16) + #endif /* __PAU_REGS_H */ diff --git a/include/pau.h b/include/pau.h index fdf85f8..0246a63 100644 --- a/include/pau.h +++ b/include/pau.h @@ -22,6 +22,7 @@ enum pau_dev_type { /* Used to expose a hardware BAR (or logical slice of it) outside skiboot */ struct pau_bar { + bool enable; uint64_t addr; uint64_t size; uint64_t cfg; |