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author | Michael Neuling <mikey@neuling.org> | 2017-07-24 10:37:27 +1000 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-07-25 15:42:30 +1000 |
commit | b4c69f3126ecbe85f415d8a6aa06efab80653cbc (patch) | |
tree | e3bad6c50ff72ed7e0c3f8fd0bc6794b83c0c07a /include | |
parent | cf960e2884027b0b2f7bedd69b767a7ddceb960a (diff) | |
download | skiboot-b4c69f3126ecbe85f415d8a6aa06efab80653cbc.zip skiboot-b4c69f3126ecbe85f415d8a6aa06efab80653cbc.tar.gz skiboot-b4c69f3126ecbe85f415d8a6aa06efab80653cbc.tar.bz2 |
phb4: Add link training trace mode
Add a mode to PHB4 to trace training process closely. This activates
as soon as PERST is deasserted and produces human readable output of
the process.
This may increase training times since it duplicates some of the
training code. This code has it's own simple checks for fence and
timeout but will fall through to the default training code once done.
Output produced, looks like the "TRACE:" lines below:
[ 3.410799664,7] PHB#0001[0:1]: FRESET: Starts
[ 3.410802000,7] PHB#0001[0:1]: FRESET: Prepare for link down
[ 3.410806624,7] PHB#0001[0:1]: FRESET: Assert skipped
[ 3.410808848,7] PHB#0001[0:1]: FRESET: Deassert
[ 3.410812176,3] PHB#0001[0:1]: TRACE: 0x0000000101000000 0ms
[ 3.417170176,3] PHB#0001[0:1]: TRACE: 0x0000100101000000 12ms presence
[ 3.436289104,3] PHB#0001[0:1]: TRACE: 0x0000180101000000 49ms training
[ 3.436373312,3] PHB#0001[0:1]: TRACE: 0x00001d0811000000 49ms trained
[ 3.436420752,3] PHB#0001[0:1]: TRACE: Link trained.
[ 3.436967856,7] PHB#0001[0:1]: LINK: Start polling
[ 3.437482240,7] PHB#0001[0:1]: LINK: Electrical link detected
[ 3.437996864,7] PHB#0001[0:1]: LINK: Link is up
[ 4.438000048,7] PHB#0001[0:1]: LINK: Link is stable
Enabled via nvram using:
nvram -p ibm,skiboot --update-config pci-tracing=true
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/phb4-regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 14e9351..932da5b 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -284,6 +284,7 @@ #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) +#define PHB_PCIE_DLP_TRAINING PPC_BIT(20) #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 |