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authorVasant Hegde <hegdevasant@linux.vnet.ibm.com>2018-01-15 14:53:51 +0530
committerStewart Smith <stewart@linux.vnet.ibm.com>2018-02-13 01:30:10 -0600
commit85f55e36bbd27fb9f75ba7cec912fd24490570ed (patch)
tree7b67d4dc3baf56e0f3ade8ed8a228cf4bb6702c2 /include
parent328af10e1c113449198373fa5d9dbbf1b66ddd7e (diff)
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ATTN: Enable flush instruction cache bit in HID register
In P9, we have to enable "flush the instruction cache" bit along with "attn instruction support" bit to trigger attention. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
-rw-r--r--include/processor.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/processor.h b/include/processor.h
index 69c5d4a..925cc7c 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -181,7 +181,7 @@
#define SPR_HID0_POWER8_HILE PPC_BIT(19)
#define SPR_HID0_POWER9_HILE PPC_BIT(4)
#define SPR_HID0_POWER8_ENABLE_ATTN PPC_BIT(31)
-#define SPR_HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
+#define SPR_HID0_POWER9_ENABLE_ATTN (PPC_BIT(2) | PPC_BIT(3))
#define SPR_HID0_POWER9_RADIX PPC_BIT(8)
/* PVR bits */