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| author | Ananth N Mavinakayanahalli <ananth@in.ibm.com> | 2014-07-24 11:47:32 +0530 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-07-25 14:10:51 +1000 |
| commit | 78a02e39e57b4441fd1901e9d08c454baedcc399 (patch) | |
| tree | 76db41d60de63bfc6e2e4c68172208b5ac3442d2 /include | |
| parent | 96a8f281500fbe70725147e2220d2091b5726600 (diff) | |
| download | skiboot-78a02e39e57b4441fd1901e9d08c454baedcc399.zip skiboot-78a02e39e57b4441fd1901e9d08c454baedcc399.tar.gz skiboot-78a02e39e57b4441fd1901e9d08c454baedcc399.tar.bz2 | |
FSP: Trigger HIR on more DISR indications
Per the Reboot and Reset/Reload HLDD, the following indicators in DISR
warrant a HIR triggered recovery (in addition to unit check which we
already handle):
a. Runtime terminated
b. Flash terminated
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fsp.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/fsp.h b/include/fsp.h index b48f4e1..1675034 100644 --- a/include/fsp.h +++ b/include/fsp.h @@ -105,7 +105,9 @@ /* Bit masks for DISR */ #define FSP_DISR_FSP_UNIT_CHECK PPC_BIT32(16) +#define FSP_DISR_FSP_RUNTIME_TERM PPC_BIT32(21) #define FSP_DISR_FSP_RR_COMPLETE PPC_BIT32(22) +#define FSP_DISR_FSP_FLASH_TERM PPC_BIT32(23) #define FSP_DISR_RUNTIME_STATE_SYNCD PPC_BIT32(24) #define FSP_DISR_DBG_IN_PROGRESS PPC_BIT32(25) #define FSP_DISR_FSP_IN_RR PPC_BIT32(26) @@ -113,6 +115,10 @@ #define FSP_DISR_CRIT_OP_IN_PROGRESS PPC_BIT32(28) #define FSP_DISR_STATUS_ACK_RXD PPC_BIT32(31) +#define FSP_DISR_HIR_TRIGGER_MASK (FSP_DISR_FSP_UNIT_CHECK | \ + FSP_DISR_FSP_RUNTIME_TERM | \ + FSP_DISR_FSP_FLASH_TERM) + /* The host version of the control register shares bits with the FSP's * control reg. Those bits are defined such that one side can set * a bit and the other side can clear it |