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| author | Frederic Barrat <fbarrat@linux.vnet.ibm.com> | 2017-08-01 14:36:13 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-04 17:13:10 +1000 |
| commit | 700611a48025c5a556bb0aa011ac81bb5d1bcbc1 (patch) | |
| tree | 28efdd8bd3814ed874be71dda5b7405c5637ca60 /include | |
| parent | 6ec0a1c0e3f57820f14e6e613d30ff7919fba2b6 (diff) | |
| download | skiboot-700611a48025c5a556bb0aa011ac81bb5d1bcbc1.zip skiboot-700611a48025c5a556bb0aa011ac81bb5d1bcbc1.tar.gz skiboot-700611a48025c5a556bb0aa011ac81bb5d1bcbc1.tar.bz2 | |
phb4: Enable PCI peer-to-peer
P9 supports PCI peer-to-peer: a PCI device can write directly to the
mmio space of another PCI device. It completely by-passes the CPU.
It requires some configuration on the PHBs involved:
1. on the initiating side, the address for the read/write operation is
in the mmio space of the target, i.e. well outside the range normally
allowed. So we disable range-checking on the TVT entry in bypass mode.
2. on the target side, we need to explicitly enable p2p by setting a
bit in a configuration register. It has the side-effect of reserving
an outbound (as seen from the CPU) store queue for p2p. Therefore we
only enable p2p on the PHBs using it, as we don't want to waste the
resource if we don't have to.
P9 supports p2p mmio writes. Reads are currently only supported if the
two devices are under the same PHB but that is expected to change in
the future, and it raises questions about intermediate switches
configuration, so we report an error for the time being.
The patch adds a new OPAL call to allow the OS to declare a p2p
(initiator, target) pair.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opal-api.h | 13 | ||||
| -rw-r--r-- | include/pci.h | 4 | ||||
| -rw-r--r-- | include/phb4-regs.h | 1 |
3 files changed, 17 insertions, 1 deletions
diff --git a/include/opal-api.h b/include/opal-api.h index 12716c5..0ff0db0 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -213,7 +213,8 @@ #define OPAL_GET_POWER_SHIFT_RATIO 154 #define OPAL_SET_POWER_SHIFT_RATIO 155 #define OPAL_SENSOR_GROUP_CLEAR 156 -#define OPAL_LAST 156 +#define OPAL_PCI_SET_P2P 157 +#define OPAL_LAST 157 /* Device tree flags */ @@ -1261,6 +1262,16 @@ enum { }; +/* PCI p2p descriptor */ +#define OPAL_PCI_P2P_ENABLE 0x1 +#define OPAL_PCI_P2P_LOAD 0x2 +#define OPAL_PCI_P2P_STORE 0x4 + +enum { + OPAL_PCI_P2P_INITIATOR = 0, + OPAL_PCI_P2P_TARGET = 1, +}; + #endif /* __ASSEMBLY__ */ #endif /* __OPAL_API_H */ diff --git a/include/pci.h b/include/pci.h index f216594..54a62fd 100644 --- a/include/pci.h +++ b/include/pci.h @@ -323,6 +323,10 @@ struct phb_ops { uint64_t pe_number); int64_t (*set_capp_recovery)(struct phb *phb); + + /* PCI peer-to-peer setup */ + void (*set_p2p)(struct phb *phb, uint64_t mode, uint64_t flags, + uint16_t pe_number); }; enum phb_type { diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 932da5b..f06a154 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -335,6 +335,7 @@ #define XPEC_NEST_STK_ERR_RPT1 0xb #define XPEC_NEST_STK_PBCQ_STAT 0xc #define XPEC_NEST_STK_PBCQ_MODE 0xd +#define XPEC_NEST_STK_PBCQ_MODE_P2P PPC_BIT(0) #define XPEC_NEST_STK_MMIO_BAR0 0xe #define XPEC_NEST_STK_MMIO_BAR0_MASK 0xf #define XPEC_NEST_STK_MMIO_BAR1 0x10 |