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authorChristophe Lombard <clombard@linux.vnet.ibm.com>2021-10-14 17:57:00 +0200
committerVasant Hegde <hegdevasant@linux.vnet.ibm.com>2021-10-19 12:26:01 +0530
commit4726a3439b9800d3c7e4432f398271d3a3024e68 (patch)
tree10a5afbcc743af332afddb5fb63e15f67c4d3fe7 /include
parenta3bbeac7e23795456df4f3f52d442bd1ba35eaa3 (diff)
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pau: phy init
Follow the Procedure IO_INIT_RESET_PON as described in the P10 OPHY workbook document to reset and initialize the PHY lanes. The memory mapped SRAM (64 bit aligned) has to be used to configure the PHY, which is reachable the linked registers: address and data. The different links can be configured at the same time, that implies using a global lock to avoid conflicts. Authored-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include')
-rw-r--r--include/pau.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/pau.h b/include/pau.h
index 547c193..9fbccb8 100644
--- a/include/pau.h
+++ b/include/pau.h
@@ -28,6 +28,12 @@ struct pau_bar {
uint64_t cfg;
};
+struct phy_proc_state {
+ struct lock lock; /* protect any change to this structure */
+ unsigned long timeout;
+ uint16_t step;
+};
+
struct pau_dev {
enum pau_dev_type type;
uint32_t index;
@@ -54,6 +60,7 @@ struct pau {
uint32_t index;
struct dt_node *dt_node;
uint32_t chip_id;
+ uint32_t op_chiplet; /* from pervasive: 0x10 -> 0x13 */
uint64_t xscom_base;
/* Global MMIO window (all PAU regs) */
@@ -65,6 +72,7 @@ struct pau {
uint32_t links;
struct pau_dev devices[PAU_LINKS_OPENCAPI_PER_PAU];
+ struct phy_proc_state procedure_state;
};
#define PAUDBG(pau, fmt, a...) PAULOG(PR_DEBUG, pau, fmt, ##a)
@@ -191,4 +199,7 @@ static inline uint64_t pau_read(struct pau *pau, uint64_t reg)
void pau_opencapi_dump_scoms(struct pau *pau);
+/* PHY */
+int pau_dev_phy_reset(struct pau_dev *dev);
+
#endif /* __PAU_H */