phb4/5: Fix PHB link width detection to avoid useless retrainings

On P9 and P10, the PCI express controller (PEC) controls a set of 16
lanes, which can be grouped to form link(s) of various width (4, 8 or
16 lanes). A PCI host bridge (PHB) is handling each link. How many
PHBs are active in each PEC is configurable per chip and vary between
2 chips in a system. Therefore PHBs have different link width.

The link width of the PHB is used to check if the link is trained
optimally and can cause link training retries if that's not the
case. We were reading the max link width of a PHB from the link
capability register of the PCI express capability of the root
bridge. But that value is always an overshoot as it needs to
accommodate any PEC configuration. It was hard to fault on P9, as a
PEC needs to be trifurcated to start noticing a difference and the
device-supported width can also mask it. But on P10, it's also
noticeable on bifurcated configuration so it's a bit easier to spot.

For example, on P10, PHB0 reports a supported width of 16 in its link
capability register because that's what is needed in case of no
furcation, but if the PEC is bifurcated or trifurcated, only 8 lanes
are wired. So we won't be able to train at more than x8. If we believe
the PHB is x16-capable, then we'll retrain the link, potentially
several times, thinking it's not optimal, which is a waste of time.

This patch finds out the real maximum link width of each PHB, which
may require to go check the PEC configuration. The logic is the same
on P9 and P10 though the hardware implementations differ slightly.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/phb4.h b/include/phb4.h
index 0bbfc92..4f1fb31 100644
--- a/include/phb4.h
+++ b/include/phb4.h
@@ -197,6 +197,7 @@ struct phb4 {
 	bool			lane_eq_en;
 	unsigned int		max_link_speed;
 	unsigned int		dt_max_link_speed;
+	unsigned int		max_link_width;
 
 	uint64_t		mrt_size;
 	uint64_t		mbt_size;