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| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:57:01 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | e89e5b9b76923ac284bb68c3083e4bd1524e450b (patch) | |
| tree | cc5e0254f63d6a6e7e41c6cefd686e91bdf7a169 /include/xscom-p10-regs.h | |
| parent | 4726a3439b9800d3c7e4432f398271d3a3024e68 (diff) | |
| download | skiboot-e89e5b9b76923ac284bb68c3083e4bd1524e450b.zip skiboot-e89e5b9b76923ac284bb68c3083e4bd1524e450b.tar.gz skiboot-e89e5b9b76923ac284bb68c3083e4bd1524e450b.tar.bz2 | |
pau: link training
Add elementary functions to handle a phb complete, fundamental and
hot resets.
For the time being, specific creset and hreset are not supported.
A complete fundamental reset is based on the following steps, in this
order:
- Place all bricks into Fence state
- Disable BARs
- Reset ODL to Power-on Values
- Set the i2c reset pin in output mode
- Initialize PHY Lanes
- Deassert ODL reset
- Clear the the i2c reset pin
- Unfence bricks
- Enable BARs
- Enable ODL training mode
Link training is also set up.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/xscom-p10-regs.h')
| -rw-r--r-- | include/xscom-p10-regs.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/include/xscom-p10-regs.h b/include/xscom-p10-regs.h index 5ca4703..51fec51 100644 --- a/include/xscom-p10-regs.h +++ b/include/xscom-p10-regs.h @@ -58,4 +58,50 @@ #define P10_ROOT_CONTROL_7 0x50017 +/* PB DLL Configuration Registers */ +#define P10_OB_ODL(ob) (0x18011000 + (ob) * 0x1000000) + +#define P10_OB_ODL_PHY_CONFIG(ob) (P10_OB_ODL(ob) + 0x0C) +#define P10_OB_ODL_PHY_CONFIG_LINK_SELECT PPC_BITMASK(56, 57) +#define P10_OB_ODL_PHY_CONFIG_DL_SELECT PPC_BITMASK(62, 63) + +#define P10_OB_ODL_PERF_MON_CONFIG(ob) (P10_OB_ODL(ob) + 0x1C) +#define P10_OB_ODL_PERF_MON_CONFIG_ENABLE PPC_BITMASK(0, 1) +#define P10_OB_ODL_PERF_MON_CONFIG_LINK0 0b10 +#define P10_OB_ODL_PERF_MON_CONFIG_LINK1 0b01 +#define P10_OB_ODL_PERF_MON_CONFIG_SIZE PPC_BITMASK(16, 23) +#define P10_OB_ODL_PERF_MON_CONFIG_SIZE16 0xFF + +#define P10_OB_ODL_PERF_MON_SELECT(ob) (P10_OB_ODL(ob) + 0x1D) +#define P10_OB_ODL_PERF_MON_SELECT_COUNTER PPC_BITMASK(0, 7) +#define P10_OB_ODL_PERF_MON_SELECT_CRC_ODL 0x44 +#define P10_OB_ODL_PERF_MON_SELECT_CRC_DLX 0x45 + +#define P10_OB_PERF_COUNTER0(ob) (P10_OB_ODL(ob) + 0x1E) +#define P10_OB_PERF_COUNTER0_LOW PPC_BITMASK(0, 31) +#define P10_OB_PERF_COUNTER0_HIGH PPC_BITMASK(32, 63) + +#define P10_OB_ODL_CONFIG(ob, brk) (P10_OB_ODL(ob) + 0x2A + brk) +#define P10_OB_ODL_CONFIG_RESET PPC_BIT(0) +#define P10_OB_ODL_CONFIG_VERSION PPC_BITMASK(2, 7) +#define P10_OB_ODL_CONFIG_TRAIN_MODE PPC_BITMASK(8, 11) +#define P10_OB_ODL_CONFIG_SUPPORTED_MODES PPC_BITMASK(12, 15) +#define P10_OB_ODL_CONFIG_X4_BACKOFF_ENABLE PPC_BIT(16) +#define P10_OB_ODL_CONFIG_PHY_CNTR_LIMIT PPC_BITMASK(20, 23) +#define P10_OB_ODL_CONFIG_DEBUG_ENABLE PPC_BIT(33) +#define P10_OB_ODL_CONFIG_FWD_PROGRESS_TIMER PPC_BITMASK(40, 43) + +#define P10_OB_ODL_STATUS(ob, brk) (P10_OB_ODL(ob) + 0x2C + brk) +#define P10_OB_ODL_STATUS_TRAINED_MODE PPC_BITMASK(0, 3) +#define P10_OB_ODL_STATUS_RX_TRAINED_LANES PPC_BITMASK(16, 23) +#define P10_OB_ODL_STATUS_TX_TRAINED_LANES PPC_BITMASK(24, 31) +#define P10_OB_ODL_STATUS_TRAINING_STATE PPC_BITMASK(49, 51) + +#define P10_OB_ODL_TRAIN_STAT(ob, brk) (P10_OB_ODL(ob) + 0x2E + brk) +#define P10_OB_ODL_TRAIN_STAT_PATTERN_B PPC_BITMASK(8, 15) + +#define P10_OB_ODL_DLX_INFO(ob, brk) (P10_OB_ODL(ob) + 0x32 + brk) + +#define P10_OB_ODL_LINK_SPEED_STATUS(ob, brk) (P10_OB_ODL(ob) + 0x34 + brk) + #endif /* __XSCOM_P10_REGS_H__ */ |