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| author | Philippe Bergheaud <felix@linux.vnet.ibm.com> | 2018-02-21 13:31:17 +0100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-03-01 20:36:53 -0600 |
| commit | a8cfb0906643a7b074a5822bb312bf7481625905 (patch) | |
| tree | 1bff51d3267f490cc20ab1c7b85198954c2f48fe /include/phb4-regs.h | |
| parent | 56a85b41d23147e7dbe6d78d5a46d13910bc8495 (diff) | |
| download | skiboot-a8cfb0906643a7b074a5822bb312bf7481625905.zip skiboot-a8cfb0906643a7b074a5822bb312bf7481625905.tar.gz skiboot-a8cfb0906643a7b074a5822bb312bf7481625905.tar.bz2 | |
phb4: set PHB CMPM registers for tunneled operations
P9 supports PCI tunneled operations (atomics and as_notify) that require
setting the PHB ASN Compare/Mask register with a 16-bit indication.
This register is currently initialized by enable_capi_mode(). But, as
tunneled operations may also work in PCI mode, the ASN Compare/Mask
register should rather be initialized in phb4_init_ioda3().
This patch also adds "ibm,phb-indications" to the device tree, to tell
Linux the values of CAPI, ASN, and NBW indications, when supported.
Tunneled operations tested by IBM in CAPI mode, by Mellanox Technologies
in PCI mode.
Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index fa585d0..16a1a74 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -71,8 +71,8 @@ #define PHB_PEST_BAR 0x1a8 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8,51) -#define PHB_PBL_ASN_CMPM 0x1C0 -#define PHB_PBL_ASN_ENABLE PPC_BIT(63) +#define PHB_ASN_CMPM 0x1C0 +#define PHB_ASN_CMPM_ENABLE PPC_BIT(63) #define PHB_CAPI_CMPM 0x1C8 #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) #define PHB_M64_UPPER_BITS 0x1f0 |