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| author | Michael Neuling <mikey@neuling.org> | 2017-08-10 16:02:53 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-11 16:37:27 +1000 |
| commit | 961547bceed3276415e1a8505093a818a44001e7 (patch) | |
| tree | 0d52d7500c3e4c2e103d69e030bba2b625148d7f /include/phb4-regs.h | |
| parent | efba98b4ae269ac41b6f56d2080e366f1c09a6d6 (diff) | |
| download | skiboot-961547bceed3276415e1a8505093a818a44001e7.zip skiboot-961547bceed3276415e1a8505093a818a44001e7.tar.gz skiboot-961547bceed3276415e1a8505093a818a44001e7.tar.bz2 | |
phb4: Enhanced PCIe training tracing
This add more details to the PCI training tracing (aka Rick Mata
mode). It enables the PCIe Link Training and Status State
Machine (LTSSM) tracing and details on speed and link width.
Output now looks like this when enabled (via nvram):
[ 1.096995141,3] PHB#0000[0:0]: TRACE:0x0000001101000000 0ms GEN1:x16:detect
[ 1.102849137,3] PHB#0000[0:0]: TRACE:0x0000102101000000 11ms presence GEN1:x16:polling
[ 1.104341838,3] PHB#0000[0:0]: TRACE:0x0000182101000000 14ms training GEN1:x16:polling
[ 1.104357444,3] PHB#0000[0:0]: TRACE:0x00001c5101000000 14ms training GEN1:x16:recovery
[ 1.104580394,3] PHB#0000[0:0]: TRACE:0x00001c5103000000 14ms training GEN3:x16:recovery
[ 1.123259359,3] PHB#0000[0:0]: TRACE:0x00001c5104000000 51ms training GEN4:x16:recovery
[ 1.141737656,3] PHB#0000[0:0]: TRACE:0x0000144104000000 87ms presence GEN4:x16:L0
[ 1.141752318,3] PHB#0000[0:0]: TRACE:0x0000154904000000 87ms trained GEN4:x16:L0
[ 1.141757964,3] PHB#0000[0:0]: TRACE: Link trained.
[ 1.096834019,3] PHB#0001[0:1]: TRACE:0x0000001101000000 0ms GEN1:x16:detect
[ 1.105578525,3] PHB#0001[0:1]: TRACE:0x0000102101000000 17ms presence GEN1:x16:polling
[ 1.112763075,3] PHB#0001[0:1]: TRACE:0x0000183101000000 31ms training GEN1:x16:config
[ 1.112778956,3] PHB#0001[0:1]: TRACE:0x00001c5081000000 31ms training GEN1:x08:recovery
[ 1.113002083,3] PHB#0001[0:1]: TRACE:0x00001c5083000000 31ms training GEN3:x08:recovery
[ 1.114833873,3] PHB#0001[0:1]: TRACE:0x0000144083000000 35ms presence GEN3:x08:L0
[ 1.114848832,3] PHB#0001[0:1]: TRACE:0x0000154883000000 35ms trained GEN3:x08:L0
[ 1.114854650,3] PHB#0001[0:1]: TRACE: Link trained.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index f06a154..59c308e 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -282,11 +282,28 @@ #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 +#define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30,35) +#define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36,39) +#define PHB_PCIE_DLP_LTSSM_TRC PPC_BITMASK(24,27) +#define PHB_PCIE_DLP_LTSSM_RESET 0 +#define PHB_PCIE_DLP_LTSSM_DETECT 1 +#define PHB_PCIE_DLP_LTSSM_POLLING 2 +#define PHB_PCIE_DLP_LTSSM_CONFIG 3 +#define PHB_PCIE_DLP_LTSSM_L0 4 +#define PHB_PCIE_DLP_LTSSM_REC 5 +#define PHB_PCIE_DLP_LTSSM_L1 6 +#define PHB_PCIE_DLP_LTSSM_L2 7 +#define PHB_PCIE_DLP_LTSSM_HOTRESET 8 +#define PHB_PCIE_DLP_LTSSM_DISABLED 9 +#define PHB_PCIE_DLP_LTSSM_LOOPBACK 10 #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) +#define PHB_PCIE_DLP_TRWCTL 0x1A80 +#define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) + #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 |