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| author | Oliver O'Halloran <oohall@gmail.com> | 2018-10-30 11:02:30 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-11-01 23:56:44 -0500 |
| commit | 9597a12ef4b3644e4b8644f659bec04ca139b7f9 (patch) | |
| tree | bc74bf641e0e0b597df9e646637ffe9012d8fc4d /include/phb4-regs.h | |
| parent | cee7ec9eae090e3e9ca6b8f07f40a9ae8164ecab (diff) | |
| download | skiboot-9597a12ef4b3644e4b8644f659bec04ca139b7f9.zip skiboot-9597a12ef4b3644e4b8644f659bec04ca139b7f9.tar.gz skiboot-9597a12ef4b3644e4b8644f659bec04ca139b7f9.tar.bz2 | |
phb4: Check for RX errors after link training
Some PHB4 PHYs can get stuck in a bad state where they are constantly
retraining the link. This happens transparently to skiboot and Linux
but will causes PCIe to be slow. Resetting the PHB4 clears the
problem.
We can detect this case by looking at the RX errors count where we
check for link stability. This patch does this by modifying the link
optimal code to check for RX errors. If errors are occurring we
retrain the link irrespective of the chip rev or card.
Normally when this problem occurs, the RX error count is maxed out at
255. When there is no problem, the count is 0. We chose 8 as the max
rx errors value to give us some margin for a few errors. There is also
a knob that can be used to set the error threshold for when we should
retrain the link. ie
nvram -p ibm,skiboot --update-config phb-rx-err-max=8
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index ef3cfa9..28f22f9 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -312,7 +312,9 @@ #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 +#define PHB_PCIE_DLP_LANE_ERR PPC_BITMASK(0,15) #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 +#define PHB_PCIE_DLP_RX_ERR_CNT PPC_BITMASK(16,23) #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 |