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| author | Vaibhav Jain <vaibhav@linux.ibm.com> | 2018-07-04 20:31:38 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-07-04 18:40:54 -0500 |
| commit | 47c09cdfe7a34843387c968ce75cea8dc578ab91 (patch) | |
| tree | 0f3495558808390e78ddcc3d139620e0cb4cc1d4 /include/phb4-regs.h | |
| parent | d6de8fe73b88f92d6a222905e1974ec73777d5e5 (diff) | |
| download | skiboot-47c09cdfe7a34843387c968ce75cea8dc578ab91.zip skiboot-47c09cdfe7a34843387c968ce75cea8dc578ab91.tar.gz skiboot-47c09cdfe7a34843387c968ce75cea8dc578ab91.tar.bz2 | |
phb4/capp: Calculate STQ/DMA read engines based on link-width for PEC
Presently in CAPI mode the number of STQ/DMA-read engines allocated on
PEC2 for CAPP is fixed to 6 and 0-30 respectively irrespective of the
PCI link width. These values are only suitable for x8 cards and
quickly run out if a x16 card is plugged to a PEC2 attached slot. This
usually manifests as CAPP reporting TLBI timeout due to these messages
getting stalled due to insufficient STQs.
To fix this we update enable_capi_mode() to check if PEC2 chiplet is
in x16 mode and if yes then we allocate 4/0-47 STQ/DMA-read engines
for the CAPP traffic.
Cc: stable # v5.7+
Fixes: 37ea3cfdc852("capi: Enable capi mode for PHB4")
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 3f87ddc..e7a190e 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -400,6 +400,12 @@ #define XETU_HV_IND_ADDR_AUTOINC PPC_BIT(2) #define XETU_HV_IND_DATA 0x1 + +/* PCI Chiplet Config Register */ +#define XPEC_PCI2_CPLT_CONF1 0x000000000F000009ULL +#define XPEC_PCI2_IOVALID_MASK PPC_BITMASK(4, 6) +#define XPEC_PCI2_IOVALID_X16 PPC_BIT(4) + /* * IODA3 on-chip tables */ |