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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-08-04 12:51:28 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:29:44 +0530 |
| commit | 3e0d7c07b7c5d627d81f7386f6f2a9027b84faf6 (patch) | |
| tree | 4e88866ce667e9cf34de770789df8eafcd7d467b /include/phb4-regs.h | |
| parent | fe2a79a6a7880e3bae91067c2c0adeafee2507e4 (diff) | |
| download | skiboot-3e0d7c07b7c5d627d81f7386f6f2a9027b84faf6.zip skiboot-3e0d7c07b7c5d627d81f7386f6f2a9027b84faf6.tar.gz skiboot-3e0d7c07b7c5d627d81f7386f6f2a9027b84faf6.tar.bz2 | |
phb5: Add register inits specific to Gen5
Update init sequence to take into account Gen5.
Define default equlization settings if HDAT is not used.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 99633e1..8ab78c3 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -295,8 +295,10 @@ #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 -#define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 -#define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 +#define PHB_PCIE_LANE_EQ_CNTL40 0x1AF0 +#define PHB_PCIE_LANE_EQ_CNTL41 0x1AF8 +#define PHB_PCIE_LANE_EQ_CNTL50 0x1B00 +#define PHB_PCIE_LANE_EQ_CNTL51 0x1B08 #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 #define PHB_PCIE_PDL_PHY_EQ_CNTL 0x1B38 |