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| author | Vaibhav Jain <vaibhav@linux.ibm.com> | 2018-07-19 13:24:59 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-07-19 03:24:49 -0500 |
| commit | 3754dba77ef5a4d72dc579e789c0a7b06af02160 (patch) | |
| tree | 1046c6b94fe26067e1982b07f8471f191f5d32bb /include/phb4-regs.h | |
| parent | 1a4aa1cb03498de236989ab8be797f0e84011fd8 (diff) | |
| download | skiboot-3754dba77ef5a4d72dc579e789c0a7b06af02160.zip skiboot-3754dba77ef5a4d72dc579e789c0a7b06af02160.tar.gz skiboot-3754dba77ef5a4d72dc579e789c0a7b06af02160.tar.bz2 | |
phb4: Reallocate PEC2 DMA-Read engines to improve GPU-Direct bandwidth
We reallocate additional 16/8 DMA-Read engines allocated to stack0/1
on PEC2 respectively. This is needed to improve bandwidth available to
the Mellanox CX5 adapter when trying to read GPU memory (GPU-Direct).
If kernel cxl driver indicates a request to allocate maximum possible
DMA read engines when calling enable_capi_mode() and card is attached
to PEC2/stack0 slot then we assume its a Mellanox CX5 adapter. We then
allocate additional 16/8 extra DMA read engines to stack0 and stack1
respectively on PEC2. This is done by populating the
XPEC_PCI_PRDSTKOVR and XPEC_NEST_READ_STACK_OVERRIDE as suggested by
the h/w team.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index d7b551f..ef3cfa9 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -347,6 +347,7 @@ #define XPEC_NEST_PBCQ_HW_CONFIG_DIS_NODAL PPC_BIT(50) #define XPEC_NEST_PBCQ_HW_CONFIG_DIS_RNNN PPC_BIT(52) #define XPEC_NEST_CAPP_CNTL 0x7 +#define XPEC_NEST_READ_STACK_OVERRIDE 0x8 /* Nest base per-stack registers */ #define XPEC_NEST_STK_PCI_NFIR 0x0 @@ -381,6 +382,7 @@ /* PCI base registers */ #define XPEC_PCI_PBAIB_HW_CONFIG 0x0 #define XPEC_PCI_CAPP_SEC_BAR 0x1 +#define XPEC_PCI_PRDSTKOVR 0x2 /* PCI base per-stack registers */ #define XPEC_PCI_STK_PCI_FIR 0x0 |