diff options
| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-01-29 10:22:07 +0100 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-02-04 14:02:34 +0530 |
| commit | 15b93a301509ba7813343540e25b47ba395674b9 (patch) | |
| tree | 6cdc4bf8dc52d967129f499ae37dace814ce9a23 /include/phb4-regs.h | |
| parent | bb4530b1f4889082dae38b562b8b7cff63ba5855 (diff) | |
| download | skiboot-15b93a301509ba7813343540e25b47ba395674b9.zip skiboot-15b93a301509ba7813343540e25b47ba395674b9.tar.gz skiboot-15b93a301509ba7813343540e25b47ba395674b9.tar.bz2 | |
phb4: Disable TCE cache line buffer
This patch implements a circumvention for HW557787. It disables the
TCE cache line buffer as, under heavy loads, there's a possibility of
an entry being re-allocated incorrectly.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index d3b0aac..b6e7787 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -110,6 +110,7 @@ #define TVT_4_PER_PE 1 #define TVT_8_PER_PE 2 #define TVT_16_PER_PE 3 +#define PHB_CTRLR_TCE_CLB_DISABLE PPC_BIT(21) #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) #define PHB_AIB_FENCE_CTRL 0x860 #define PHB_TCE_TAG_ENABLE 0x868 |