hw: Introduce npu3

POWER9P systems have been upgraded with NVLink 3.0 interconnects. The
underlying hardware is fundamentally different--each POWER9 chip has

        (1 NPU) * (3 stacks) * (2 bricks) = (6 links)

Where in each POWER9P chip, there are

        (3 NPUs) * (4 bricks) = (12 links)

This flatter hierarchy simplifies the firmware implementation a bit, but
also prevents sharing much common code with npu2.

As in previous versions, initialize the hardware and expose each link to
the OS as a virtual PCIe device. This initial support covers NVLink
devices only, with OpenCAPI to follow.

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/pci.h b/include/pci.h
index c7c15d0..b840409 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -353,6 +353,7 @@ enum phb_type {
 	phb_type_pcie_v4,
 	phb_type_npu_v2,
 	phb_type_npu_v2_opencapi,
+	phb_type_npu_v3,
 };