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| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:56:54 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | 882e867012a8c4af8a7bbd42b93816b2a2f3b827 (patch) | |
| tree | ce5e90dbd3c61bcacc0b2f9476c14638d625b27f /include/pci.h | |
| parent | 8baea29fdeaa5eab26c1ca6e3b88e18a3387be96 (diff) | |
| download | skiboot-882e867012a8c4af8a7bbd42b93816b2a2f3b827.zip skiboot-882e867012a8c4af8a7bbd42b93816b2a2f3b827.tar.gz skiboot-882e867012a8c4af8a7bbd42b93816b2a2f3b827.tar.bz2 | |
pau: create phb
Implement the necessary operations for the OpenCAPI PHB type and
inform the device-tree properties associated.
The OpenCapi PCI config Addr/Data registers are reachable through
the Generation-ID Registers MMIO BARS.
The Config Address and Data registers are located at the following offsets
from the AFU Config BAR plus 320 KB.
• Config Address for Brick 0 – Offset 0
• Config Data for Brick 0 – Offsets:
◦ 128 – 4-byte config register
• Config Address for Brick 1 – Offset 256
• Config Data for Brick 1 – Offsets:
◦ 384 – 4-byte config register
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h index 8d46721..caae744 100644 --- a/include/pci.h +++ b/include/pci.h @@ -352,6 +352,7 @@ enum phb_type { phb_type_pcie_v4, phb_type_npu_v2, phb_type_npu_v2_opencapi, + phb_type_pau_opencapi, }; /* Generic PCI NVRAM flags */ |