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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2019-04-05 16:33:01 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-04-09 10:50:55 +1000 |
| commit | f8dfd699f5844ce7e7934beb5c9a4fe139d22250 (patch) | |
| tree | 154a50ff20d01d8f2064ff6030761dcfe8357bf9 /include/npu2-regs.h | |
| parent | fa97373f3274de5239124db5c4039a7517d9344c (diff) | |
| download | skiboot-f8dfd699f5844ce7e7934beb5c9a4fe139d22250.zip skiboot-f8dfd699f5844ce7e7934beb5c9a4fe139d22250.tar.gz skiboot-f8dfd699f5844ce7e7934beb5c9a4fe139d22250.tar.bz2 | |
hw/npu2: Setup an error interrupt on some opencapi FIRs
Many errors reported in the NPU FIR2 register, mostly catching
unexpected errors on the opencapi link are defined as 'brick fatal' in
the workbook, yet the default action is set to system checkstop. It's
possible to see those errors during AFU development, where the AFU may
send unexpected packets on the link, therefore triggering those
errors. Checkstopping the system in this case is clearly extreme, as
the error could be contained to the brick and proper analysis of a
checkstop is not trivial outside of a bringup environment.
This patch changes the default action of those errors so that the NPU
will raise an interrupt instead. Follow-up patches will log
proper information so that the error can be debugged and linux can
catch the event.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index ca31109..939a23f 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -480,10 +480,13 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_MISC_IRQ_LOG13 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x368) #define NPU2_MISC_IRQ_LOG14 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x370) #define NPU2_MISC_IRQ_LOG15 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x378) +#define NPU2_MISC_FENCE_ENABLE2 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x400) #define NPU2_MISC_IRQ_ENABLE2 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x408) /* Misc register, direct access only */ -#define NPU2_MISC_FIR_MASK1 0x2C43 +#define NPU2_MISC_FIR0_MASK 0x2C03 +#define NPU2_MISC_FIR1_MASK 0x2C43 +#define NPU2_MISC_FIR2_MASK 0x2C83 /* ATS block registers */ #define NPU2_ATS_PMU_CTL NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_ATS, 0x000) |