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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-11-14 11:28:42 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-15 01:03:53 -0600 |
| commit | d123203cfa9f03814c3939b0f50153095dbdc6e4 (patch) | |
| tree | deeb6c4344fbbd1d60a80424b766194d6ba425f3 /include/npu2-regs.h | |
| parent | c76636f3d73fbbc3a1f56ca085eb80f9e56d0411 (diff) | |
| download | skiboot-d123203cfa9f03814c3939b0f50153095dbdc6e4.zip skiboot-d123203cfa9f03814c3939b0f50153095dbdc6e4.tar.gz skiboot-d123203cfa9f03814c3939b0f50153095dbdc6e4.tar.bz2 | |
Revert "npu2: hw-procedures: Enable low power mode"
As it turns out, low power mode is not yet ready for prime time. We
shouldn't write the low power config register until it is.
This reverts commit a05054c53a37850a2118d01fcf6669ebb10d1a33.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 2d3fc3e..fdaad19 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -257,12 +257,6 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_NTL_MISC_CFG1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0C0) #define NPU2_NTL_SCRATCH1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0D0) #define NPU2_NTL_LOW_POWER_CFG(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0E0) -#define NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE PPC_BIT(0) -#define NPU2_NTL_LOW_POWER_CFG_ONLY_MODE PPC_BIT(1) -#define NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG PPC_BITMASK(2,7) -#define NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH PPC_BITMASK(8,19) -#define NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH PPC_BITMASK(20,31) -#define NPU2_NTL_LOW_POWER_CFG_CNT_THRESH PPC_BITMASK(32,43) #define NPU2_NTL_DBG_INHIBIT_CFG(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x220) #define NPU2_NTL_DISPLAY_CTL(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x280) #define NPU2_NTL_DISPLAY_DATA0(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x288) |