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| author | Andrew Donnellan <andrew.donnellan@au1.ibm.com> | 2018-03-01 18:57:14 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-03-01 20:17:54 -0600 |
| commit | 9db58b1e5c031782c442f92775ee75326a7be1b3 (patch) | |
| tree | 14360368a1ce60a349192bd20d0ff54a4b67ed64 /include/npu2-regs.h | |
| parent | b5f1fd30ef56290a6171c79b71bbecb3516e7cf7 (diff) | |
| download | skiboot-9db58b1e5c031782c442f92775ee75326a7be1b3.zip skiboot-9db58b1e5c031782c442f92775ee75326a7be1b3.tar.gz skiboot-9db58b1e5c031782c442f92775ee75326a7be1b3.tar.bz2 | |
npu2-hw-procedures: Add support for OpenCAPI PHY link training
Unlike NVLink, which uses the pci-virt framework to fake a PCI
configuration space for NVLink devices, the OpenCAPI device model presents
us with a real configuration space handled by the device over the OpenCAPI
link.
As a result, we have to train the OpenCAPI link in skiboot before we do PCI
probing, so that config space can be accessed, rather than having link
training being triggered by the Linux driver.
Add some helper functions to wrap the existing NVLink PHY training sequence
so we can easily run it within skiboot.
Additionally, we add OpenCAPI-specific lane settings, and a function to
"bump" lanes that haven't trained properly (this process isn't documented
in the workbook, but the hardware experts assure us that this improves link
training reliability...) We also support the PRBS31 pattern that's used for
bringup and test purposes.
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 08c4f92..7ef5994 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -668,4 +668,10 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE PPC_BIT(52) #define PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE PPC_BIT(57) +#define OB0_ODL0_TRAINING_STATUS 0x901082E +#define OB0_ODL1_TRAINING_STATUS 0x901082F +#define OB3_ODL0_TRAINING_STATUS 0xC01082E +#define OB3_ODL1_TRAINING_STATUS 0xC01082F +#define OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B PPC_BITMASK(8, 15) + #endif /* __NPU2_REGS_H */ |