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| author | Sam Bobroff <sam.bobroff@au1.ibm.com> | 2017-08-22 09:58:11 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-12 22:55:12 -0500 |
| commit | 0b2906e50e1f7b96c67534ee7a186b7d99aed820 (patch) | |
| tree | 0734ff5a1e77a658d5c6610a2dcb1e1d457d8760 /include/npu2-regs.h | |
| parent | 80547fc3a5c30de4e1aca69b364bc06793ea61dc (diff) | |
| download | skiboot-0b2906e50e1f7b96c67534ee7a186b7d99aed820.zip skiboot-0b2906e50e1f7b96c67534ee7a186b7d99aed820.tar.gz skiboot-0b2906e50e1f7b96c67534ee7a186b7d99aed820.tar.bz2 | |
npu2: Enable recoverable data link (no-stall) interrupts
Allow the NPU2 to trigger "recoverable data link" interrupts.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Acked-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 86e2658..759404c 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -286,6 +286,16 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_MISC_ERR_RPT_HOLD NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x020) #define NPU2_MISC_ERR_RPT_MASK NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x028) #define NPU2_MISC_CFG NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x030) +#define NPU2_MISC_CFG_CONFIG_SYNC_WAIT PPC_BITMASK(0,4) +#define NPU2_MISC_CFG_PERF_CONFIG_ENABLE PPC_BIT(5) +#define NPU2_MISC_CFG_PERF_CONFIG_PE_MASK PPC_BIT(6) +#define NPU2_MISC_CFG_PERF_CONFIG_PE_MATCH PPC_BITMASK(7,10) +#define NPU2_MISC_CFG_IPI_PS PPC_BIT(11) +#define NPU2_MISC_CFG_IPI_PS_4K 0 +#define NPU2_MISC_CFG_IPI_PS_64K 1 +#define NPU2_MISC_CFG_IPI_OS PPC_BIT(12) +#define NPU2_MISC_CFG_IPI_OS_AIX 0 +#define NPU2_MISC_CFG_IPI_OS_LINUX 1 #define NPU2_MISC_INHIBIT_CFG NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x038) #define NPU2_MISC_FREEZE_ENABLE0 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x040) #define NPU2_MISC_FREEZE_ENABLE1 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x048) |