diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2021-08-04 12:50:40 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 11:51:25 +0530 |
| commit | 891ed8df672ddc3a38b4629aa4087f9930e1669d (patch) | |
| tree | 02f93eebfb1ff97059d5e85cd6d29342e657b7c3 /include/chip.h | |
| parent | 65714f47fb7e4d0dbf4b7d2befb5c5e86014befd (diff) | |
| download | skiboot-891ed8df672ddc3a38b4629aa4087f9930e1669d.zip skiboot-891ed8df672ddc3a38b4629aa4087f9930e1669d.tar.gz skiboot-891ed8df672ddc3a38b4629aa4087f9930e1669d.tar.bz2 | |
Initial POWER10 enablement
Co-authored-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Co-authored-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Co-authored-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Co-authored-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/chip.h')
| -rw-r--r-- | include/chip.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/include/chip.h b/include/chip.h index 4deb961..8bc48ba 100644 --- a/include/chip.h +++ b/include/chip.h @@ -100,10 +100,58 @@ #define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3) +#define P10_PIR2FUSEDCOREID(pir) P9_PIR2FUSEDCOREID(pir) +#define P10_PIRFUSED2NORMALCOREID(pir) P9_PIRFUSED2NORMALCOREID(pir) +#define P10_PIRFUSED2NORMALTHREADID(pir) P9_PIRFUSED2NORMALTHREADID(pir) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) +/* + * P10 PIR + * ------- + * + * PIR layout: + * + * | 49| 50| 51| 52| 53| 54| 55| 56| 57| 58| 59| 60| 61| 62| 63| + * |Spare ID |Topology ID |Sp. |Quad ID |Core ID |Thread ID| + * + * Bit 56 is a spare quad ID. In big-core mode, thread ID extends to bit 61. + * + * P10 GCID + * -------- + * + * - Global chip ID is also called Topology ID. + * - Node ID is called Group ID (? XXX P10). + * + * Global chip ID is a 4 bit number. + * + * There is a topology mode bit that can be 0 or 1, which changes GCID mapping. + * + * Topology mode 0: + * NodeID ChipID + * | | | + * |____|____|____|____| + * + * Topology mode 1: + * NodeID ChipID + * | | | + * |____|____|____|____| + */ +#define P10_PIR2GCID(pir) (((pir) >> 8) & 0xf) + +#define P10_PIR2COREID(pir) (((pir) >> 2) & 0x3f) + +#define P10_PIR2THREADID(pir) ((pir) & 0x3) + +// XXX P10 These depend on the topology mode, how to get that (system type?) +#define P10_GCID2NODEID(gcid, mode) ((mode) == 0 ? ((gcid) >> 1) & 0x7 : ((gcid) >> 2) & 0x3) +#define P10_GCID2CHIPID(gcid, mode) ((mode) == 0 ? (gcid) & 0x1 : (gcid) & 0x3) + +/* P10 specific ones mostly used by XIVE */ +#define P10_PIR2LOCALCPU(pir) ((pir) & 0xff) +#define P10_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) struct dt_node; struct centaur_chip; @@ -123,6 +171,7 @@ enum proc_chip_type { PROC_CHIP_P9_NIMBUS, PROC_CHIP_P9_CUMULUS, PROC_CHIP_P9P, + PROC_CHIP_P10, }; /* Simulator quirks */ |