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authorAlistair Popple <alistair@popple.id.au>2018-01-24 14:44:57 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2018-01-30 20:42:38 -0600
commit91f3e391f27aa90ee383e49683cef9926b99a08c (patch)
treeb577fd0545f55b971b8a6f3e5de1f81abd1fac6a /hw
parent0e2541f1c6648d20174b6fe080649cee828a43a3 (diff)
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npu2-hw-procedures.c: Power up lanes during ntl reset
Newer versions of Hostboot will not power up the NVLink PHY lanes by default. The phy_reset procedure already powers up the lanes but they also need to be powered up in order to access the DL. The reset_ntl procedure is called by the device driver to bring the DL out of reset and get it into a working state. Therefore we also need to add lane and clock power up to the reset_ntl procedure. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/npu2-hw-procedures.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index 1318e86..a43952d 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -236,9 +236,22 @@ static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val)
static uint32_t reset_ntl(struct npu2_dev *ndev)
{
uint64_t val;
+ int lane;
set_iovalid(ndev, true);
+ /* Power on clocks */
+ phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0);
+ phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1);
+ phy_write(ndev, &NPU2_PHY_TX_CLKDIST_PDWN, 0);
+ phy_write(ndev, &NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN, 0);
+
+ FOR_EACH_LANE(ndev, lane) {
+ phy_write_lane(ndev, &NPU2_PHY_RX_LANE_ANA_PDWN, lane, 0);
+ phy_write_lane(ndev, &NPU2_PHY_RX_LANE_DIG_PDWN, lane, 0);
+ phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
+ }
+
/* Write PRI */
val = SETFIELD(PPC_BITMASK(0,1), 0ull, obus_brick_index(ndev));
npu2_write_mask(ndev->npu, NPU2_NTL_PRI_CFG(ndev), val, -1ULL);