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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-08-04 12:51:33 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:30:37 +0530 |
| commit | 5232a9038a0a95f8d23549038ab791ac97c6a4ff (patch) | |
| tree | 4cc041fde04f195edefe7bf7de15e91e778c2d83 /hw | |
| parent | 23b7d5080877e6c86e4e2b82141d1362d7d45251 (diff) | |
| download | skiboot-5232a9038a0a95f8d23549038ab791ac97c6a4ff.zip skiboot-5232a9038a0a95f8d23549038ab791ac97c6a4ff.tar.gz skiboot-5232a9038a0a95f8d23549038ab791ac97c6a4ff.tar.bz2 | |
phb5: Fix PHB max link speed definition on P10
Not all PHBs are capable of GEN5 speed on P10. In all PEC
configurations, the first PHB is the only one which can handle GEN5.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/phb4.c | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -3011,10 +3011,10 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) chip = get_chip(p->chip_id); hw_max_link_speed = 4; - if (is_phb5()) + if (is_phb5() && (p->index == 0 || p->index == 3)) hw_max_link_speed = 5; - /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> GEN4 */ + /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> hw default */ max_link_speed = hw_max_link_speed; if (p->rev == PHB4_REV_NIMBUS_DD20 && ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0) |