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author | Cédric Le Goater <clg@kaod.org> | 2021-08-04 12:51:15 +0530 |
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committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:27:41 +0530 |
commit | 47f46e5ff3f816b135b65e210aff65d9194698fa (patch) | |
tree | e3168e4e6f89181f302794280427ed42585b449e /hw | |
parent | 2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2 (diff) | |
download | skiboot-47f46e5ff3f816b135b65e210aff65d9194698fa.zip skiboot-47f46e5ff3f816b135b65e210aff65d9194698fa.tar.gz skiboot-47f46e5ff3f816b135b65e210aff65d9194698fa.tar.bz2 |
psi/p10: Introduce xive2_source_mask()
Commit fa161cd89fbf ("hw/psi-p9: Mask OPAL-owned LSIs without
handlers") introduced xive_source_mask(). Do the same for P10.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/psi.c | 11 | ||||
-rw-r--r-- | hw/xive2.c | 7 |
2 files changed, 17 insertions, 1 deletions
@@ -564,7 +564,16 @@ static void psi_p9_mask_unhandled_irq(struct irq_source *is, uint32_t isn) * have a handler for the interrupt then it needs to be masked to * prevent the IRQ from locking up the thread which handles it. */ - xive_source_mask(is, isn); + switch (proc_gen) { + case proc_gen_p9: + xive_source_mask(is, isn); + break; + case proc_gen_p10: + xive2_source_mask(is, isn); + return; + default: + assert(false); + } } @@ -2531,6 +2531,13 @@ static char *xive_source_name(struct irq_source *is, uint32_t isn) return s->orig_ops->name(is, isn); } +void xive2_source_mask(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + xive_update_irq_mask(s, isn - s->esb_base, true); +} + static const struct irq_source_ops xive_irq_source_ops = { .interrupt = xive_source_interrupt, .attributes = xive_source_attributes, |