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author | Cédric Le Goater <clg@kaod.org> | 2020-11-04 23:20:56 +0100 |
---|---|---|
committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2020-11-27 15:37:15 +0530 |
commit | b6be076b1ef1cb4e752b2ca5d6e0c0c8223e801a (patch) | |
tree | 24102e5e1607a26a0bba277d690b3c7280f63468 /hw/xive.c | |
parent | 73bda5eff300a6d6f1a548942d878de48d034341 (diff) | |
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xive/p9: Introduce XIVE_ESB_PAGE_SIZE
Rename XIVE_ESB_SIZE to XIVE_ESB_PAGE_SIZE in the xive/p9 driver to
be consistent with the xive2/p10 driver.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw/xive.c')
-rw-r--r-- | hw/xive.c | 16 |
1 files changed, 8 insertions, 8 deletions
@@ -157,7 +157,7 @@ /* Use 64K for everything by default */ #define XIVE_ESB_SHIFT (16 + 1) /* trigger + mgmt pages */ -#define XIVE_ESB_SIZE (1ul << XIVE_ESB_SHIFT) /* 2 pages */ +#define XIVE_ESB_PAGE_SIZE (1ul << XIVE_ESB_SHIFT) /* 2 pages */ /* Max number of EQs. We allocate an indirect table big enough so * that when fully populated we can have that many EQs. @@ -1102,7 +1102,7 @@ static void xive_scrub_workaround_eq(struct xive *x, uint32_t block __unused, ui /* EQ variant of the workaround described in __xive_cache_scrub(), * a simple non-side effect load from ESn will do */ - mmio = x->eq_mmio + idx * XIVE_ESB_SIZE; + mmio = x->eq_mmio + idx * XIVE_ESB_PAGE_SIZE; /* Ensure the above has returned before we do anything else * the XIVE store queue is completely empty @@ -1944,7 +1944,7 @@ void *xive_get_trigger_port(uint32_t girq) girq >= x->int_ipi_top) return NULL; - return x->esb_mmio + idx * XIVE_ESB_SIZE; + return x->esb_mmio + idx * XIVE_ESB_PAGE_SIZE; } } @@ -2719,7 +2719,7 @@ static void xive_ipi_init(struct xive *x, struct cpu_thread *cpu) static void xive_ipi_eoi(struct xive *x, uint32_t idx) { - uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_SIZE; + uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_PAGE_SIZE; uint8_t eoi_val; /* For EOI, we use the special MMIO that does a clear of both @@ -2736,7 +2736,7 @@ static void xive_ipi_eoi(struct xive *x, uint32_t idx) static void xive_ipi_trigger(struct xive *x, uint32_t idx) { - uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_SIZE; + uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_PAGE_SIZE; xive_vdbg(x, "Trigger IPI 0x%x\n", idx); @@ -2965,7 +2965,7 @@ static void xive_init_cpu_emulation(struct xive_cpu_state *xs, xs->eqgen = 0; x = xive_from_vc_blk(xs->eq_blk); assert(x); - xs->eqmmio = x->eq_mmio + (xs->eq_idx + XIVE_EMULATION_PRIO) * XIVE_ESB_SIZE; + xs->eqmmio = x->eq_mmio + (xs->eq_idx + XIVE_EMULATION_PRIO) * XIVE_ESB_PAGE_SIZE; } static void xive_init_cpu_exploitation(struct xive_cpu_state *xs) @@ -3837,7 +3837,7 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, } if (out_qeoi_page) { *out_qeoi_page = - cpu_to_be64((uint64_t)x->eq_mmio + idx * XIVE_ESB_SIZE); + cpu_to_be64((uint64_t)x->eq_mmio + idx * XIVE_ESB_PAGE_SIZE); } if (out_qflags) { *out_qflags = 0; @@ -5028,7 +5028,7 @@ static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir) xs->eqbuf[(xs->eqptr + 2) & xs->eqmsk], xs->eqbuf[(xs->eqptr + 3) & xs->eqmsk]); - mm = xs->xive->esb_mmio + GIRQ_TO_IDX(xs->ipi_irq) * XIVE_ESB_SIZE; + mm = xs->xive->esb_mmio + GIRQ_TO_IDX(xs->ipi_irq) * XIVE_ESB_PAGE_SIZE; pq = in_8(mm + 0x10800); if (xive_get_irq_targetting(xs->ipi_irq, &ipi_target, NULL, NULL)) prlog(PR_INFO, "CPU[%04x]: IPI #%08x PQ=%x target=%08x\n", |