diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-10-01 08:59:53 +0200 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-11-04 10:52:47 +1100 |
| commit | ad7e9a67c4e4a39ce0605d45c55728404c66535e (patch) | |
| tree | 24f8c0f875329ac6f69bd96ddb2c256f33197faf /hw/xive.c | |
| parent | a10f1502a20b5fae6d38e262de3729619a3f886d (diff) | |
| download | skiboot-ad7e9a67c4e4a39ce0605d45c55728404c66535e.zip skiboot-ad7e9a67c4e4a39ce0605d45c55728404c66535e.tar.gz skiboot-ad7e9a67c4e4a39ce0605d45c55728404c66535e.tar.bz2 | |
xive/p9: obsolete OPAL_XIVE_IRQ_SHIFT_BUG flags
These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0
processors.
HW395455 P9/PHB4: Wrong Interrupt ESB CI Load Opcode Location in 64K
page mode
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw/xive.c')
| -rw-r--r-- | hw/xive.c | 7 |
1 files changed, 0 insertions, 7 deletions
@@ -2219,9 +2219,6 @@ static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked) else offset = 0xc00; /* PQ = 00 */ - if (s->flags & XIVE_SRC_SHIFT_BUG) - offset <<= 4; - in_be64(mmio_base + offset); } @@ -2404,8 +2401,6 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn) in_be64(mmio_base); else { offset = 0xc00; - if (s->flags & XIVE_SRC_SHIFT_BUG) - offset <<= 4; eoi_val = in_be64(mmio_base + offset); xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n", isn, eoi_val); @@ -3602,8 +3597,6 @@ static uint64_t xive_convert_irq_flags(uint64_t iflags) if (iflags & XIVE_SRC_LSI) oflags |= OPAL_XIVE_IRQ_LSI; - if (iflags & XIVE_SRC_SHIFT_BUG) - oflags |= OPAL_XIVE_IRQ_SHIFT_BUG; return oflags; } |