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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-06-25 11:49:17 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-06-30 15:05:54 +0530 |
| commit | 6cc4cf04a5ea3e317d3174175f171bcc46cf8d5c (patch) | |
| tree | d0553c2bd7d388e5467b17b772bd5e6843809dd5 /hw/vas.c | |
| parent | 8545bb2ac8e0e17af29f149745e4798e86821d36 (diff) | |
| download | skiboot-6cc4cf04a5ea3e317d3174175f171bcc46cf8d5c.zip skiboot-6cc4cf04a5ea3e317d3174175f171bcc46cf8d5c.tar.gz skiboot-6cc4cf04a5ea3e317d3174175f171bcc46cf8d5c.tar.bz2 | |
core/mce: POWER9 fix machine check decoding of async errors
Async machine check errors due to bad real address from store or
foreign link time out comes with the load/store bit (PPC bit 42)
set in SRR1 but the cause is set in SRR1 not DSISR, unlike other
errors that have the load/store bit set.
This behaviour was omitted from the POWER9 User Manual but it is
confirmed to be the expected one. Update the machine check decoder
to match.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw/vas.c')
0 files changed, 0 insertions, 0 deletions