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| author | Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> | 2017-09-15 17:51:00 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-19 04:16:53 -0500 |
| commit | 56a945e8deaba44ce2659aeeb941270b944adc41 (patch) | |
| tree | 16b8dc13c28a30e1721577bbe9acef1e382503e5 /hw/slw.c | |
| parent | d2c82baae887568e29017e0a2902db7e51284c5f (diff) | |
| download | skiboot-56a945e8deaba44ce2659aeeb941270b944adc41.zip skiboot-56a945e8deaba44ce2659aeeb941270b944adc41.tar.gz skiboot-56a945e8deaba44ce2659aeeb941270b944adc41.tar.bz2 | |
SLW: Allow deep states if homer address is known
Use a common variable has_wakeup_engine instead of has_slw to tell if
the
a) SLW image is populated in case of power8
b) CME image is populated in case of power9
Currently we expect CME to be loaded if homer address is known ( except
for simulators)
Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/slw.c')
| -rw-r--r-- | hw/slw.c | 23 |
1 files changed, 17 insertions, 6 deletions
@@ -813,7 +813,7 @@ void add_cpu_idle_state_properties(void) int nr_states; bool can_sleep = true; - bool has_slw = true; + bool has_wakeup_engine = true; bool has_stop_inst = false; u8 i; @@ -906,9 +906,20 @@ void add_cpu_idle_state_properties(void) nr_states = ARRAY_SIZE(power7_cpu_idle_states); } - /* Enable deep idle states only if slw image is intact */ - has_slw = (chip->slw_base && chip->slw_bar_size && - chip->slw_image_size); + /* + * Enable deep idle states only if : + * P8 : slw image is intact + * P9 : homer_base is set + */ + if (!(proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)) { + if (proc_gen == proc_gen_p9) + has_wakeup_engine = !!(chip->homer_base); + else /* (proc_gen == proc_gen_p8) */ + has_wakeup_engine = (chip->slw_base && chip->slw_bar_size && + chip->slw_image_size); + } else { + has_wakeup_engine = false; + } /* * Currently we can't append strings and cells to dt properties. @@ -936,7 +947,7 @@ void add_cpu_idle_state_properties(void) if (has_stop_inst) { /* Power 9 / POWER ISA 3.0 */ supported_states_mask = OPAL_PM_STOP_INST_FAST; - if (has_slw) + if (has_wakeup_engine) supported_states_mask |= OPAL_PM_STOP_INST_DEEP; } else { /* Power 7 and Power 8 */ @@ -944,7 +955,7 @@ void add_cpu_idle_state_properties(void) if (can_sleep) supported_states_mask |= OPAL_PM_SLEEP_ENABLED | OPAL_PM_SLEEP_ENABLED_ER1; - if (has_slw) + if (has_wakeup_engine) supported_states_mask |= OPAL_PM_WINKLE_ENABLED; } for (i = 0; i < nr_states; i++) { |