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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-08-04 12:51:31 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:30:20 +0530 |
| commit | 1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e (patch) | |
| tree | 7d5d209d7a21096c80ec7f1ff9c3714cd536dd2b /hw/phb4.c | |
| parent | 6af8ac2e00cddcdbdf673b3ea3ead9453c5445ba (diff) | |
| download | skiboot-1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e.zip skiboot-1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e.tar.gz skiboot-1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e.tar.bz2 | |
phb4: Cleanup PEC config discovery in CAPI mode
Small cleanup when reading the PEC config when setting up CAPI, in
preparation for P10. Scom addresses vary between P9 and P10 and we'll
be accessing more than one PCI chiplet. No functional change.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw/phb4.c')
| -rw-r--r-- | hw/phb4.c | 17 |
1 files changed, 9 insertions, 8 deletions
@@ -4282,7 +4282,7 @@ static int64_t phb4_get_capp_info(int chip_id, struct phb *phb, static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) { - uint64_t reg; + uint64_t addr, reg; uint32_t offset; uint8_t link_width_x16 = 1; @@ -4293,9 +4293,10 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) /* Check if PEC2 is in x8 or x16 mode. * PEC0 is always in x16 */ - xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, ®); - link_width_x16 = ((reg & XPEC_PCI2_IOVALID_MASK) == - XPEC_PCI2_IOVALID_X16); + addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET; + xscom_read(p->chip_id, addr, ®); + link_width_x16 = ((reg & XPEC_P9_PCI_IOVALID_MASK) == + XPEC_P9_PCI_IOVALID_X16); } /* APC Master PowerBus Control Register */ @@ -4515,7 +4516,7 @@ static void phb4_init_capp_errors(struct phb4 *p) static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, uint32_t capp_eng) { - uint64_t reg, start_addr, end_addr, stq_eng, dma_eng; + uint64_t addr, reg, start_addr, end_addr, stq_eng, dma_eng; uint64_t mbt0, mbt1; int i, window_num = -1; @@ -4553,9 +4554,9 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, if (p->index == CAPP1_PHB_INDEX) { /* Check if PEC is in x8 or x16 mode */ - xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, ®); - - if ((reg & XPEC_PCI2_IOVALID_MASK) == XPEC_PCI2_IOVALID_X16) { + addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET; + xscom_read(p->chip_id, addr, ®); + if ((reg & XPEC_P9_PCI_IOVALID_MASK) == XPEC_P9_PCI_IOVALID_X16) { /* PBCQ is operating as a x16 stack * - The maximum number of engines give to CAPP will be * 14 and will be assigned in the order of STQ 15 to 2. |