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author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2018-06-13 16:22:10 +1000 |
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committer | Stewart Smith <stewart@linux.ibm.com> | 2018-06-18 22:13:43 -0500 |
commit | fca2b2b839a673a1e52fc6b19ee6d33b2dfbc003 (patch) | |
tree | aba25ad3fbc63a4cfe3a55a0fb717f45020b6bb4 /hw/npu2.c | |
parent | 35cd7a379b935c74c184f4270c332b1ef85174a8 (diff) | |
download | skiboot-fca2b2b839a673a1e52fc6b19ee6d33b2dfbc003.zip skiboot-fca2b2b839a673a1e52fc6b19ee6d33b2dfbc003.tar.gz skiboot-fca2b2b839a673a1e52fc6b19ee6d33b2dfbc003.tar.bz2 |
npu2: Reset NVLinks on hot reset
This effectively fences GPU RAM on GPU reset so the host system
does not have to crash every time we stop a KVM guest with a GPU
passed through.
Suggested-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'hw/npu2.c')
-rw-r--r-- | hw/npu2.c | 14 |
1 files changed, 14 insertions, 0 deletions
@@ -1092,6 +1092,20 @@ static int64_t npu2_get_power_state(struct pci_slot *slot __unused, uint8_t *val static int64_t npu2_hreset(struct pci_slot *slot __unused) { + struct npu2 *p; + int i; + struct npu2_dev *ndev; + + p = phb_to_npu2_nvlink(slot->phb); + NPU2INF(p, "Hreset PHB state\n"); + + for (i = 0; i < p->total_devices; i++) { + ndev = &p->devices[i]; + if (ndev) { + NPU2DEVINF(ndev, "Resetting device\n"); + reset_ntl(ndev); + } + } return OPAL_SUCCESS; } |