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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2019-11-22 11:04:22 +1100 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-12-04 14:18:58 +1100 |
| commit | 9be9a77a8352aee0bb74ac0d79f55e1238f76285 (patch) | |
| tree | 86067e61bfb6037cc6e95e832bd4548eb602eb3a /hw/npu2-hw-procedures.c | |
| parent | 2a63db6511b63a75efe820f90bb7972afc2fcdef (diff) | |
| download | skiboot-9be9a77a8352aee0bb74ac0d79f55e1238f76285.zip skiboot-9be9a77a8352aee0bb74ac0d79f55e1238f76285.tar.gz skiboot-9be9a77a8352aee0bb74ac0d79f55e1238f76285.tar.bz2 | |
npu2: Clear fence on all bricks
A bug in the NVidia driver can cause an UR HMI which fences bricks
(links). At the moment we clear fence status only for bricks of a specific
devices, however this does not appear to be enough and we need to clear
fences for all bricks. This is ok as we do not allow using GPUs
individually anyway.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw/npu2-hw-procedures.c')
| -rw-r--r-- | hw/npu2-hw-procedures.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 3bb08d2..1f82b11 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -264,8 +264,8 @@ static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val) /* Procedure 1.2.1 - Reset NPU/NDL */ uint32_t reset_ntl(struct npu2_dev *ndev) { - uint64_t val; - int lane; + uint64_t val, check; + int lane, i; set_iovalid(ndev, true); @@ -283,10 +283,17 @@ uint32_t reset_ntl(struct npu2_dev *ndev) /* Clear fence state for the brick */ val = npu2_read(ndev->npu, NPU2_MISC_FENCE_STATE); - if (val & PPC_BIT(ndev->brick_index)) { - NPU2DEVINF(ndev, "Clearing brick fence\n"); - val = PPC_BIT(ndev->brick_index); + if (val) { + NPU2DEVINF(ndev, "Clearing all bricks fence\n"); npu2_write(ndev->npu, NPU2_MISC_FENCE_STATE, val); + for (i = 0, check = 0; i < 4096; i++) { + check = npu2_read(ndev->npu, NPU2_NTL_CQ_FENCE_STATUS(ndev)); + if (!check) + break; + } + if (check) + NPU2DEVERR(ndev, "Clearing NPU2_MISC_FENCE_STATE=0x%llx timeout, current=0x%llx\n", + val, check); } /* Write PRI */ |