diff options
| author | Russell Currey <ruscur@russell.cc> | 2016-01-18 16:59:40 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-01-21 11:59:47 +1100 |
| commit | 04b200ce1eaaedaf425a49cc5369941fd837331d (patch) | |
| tree | 5ee1d7e2721c6c6fd0d06f9dcbfc65929907cdc7 /hw/npu.c | |
| parent | 3e10683f4a0a6d6a71d4a93b7dcdb3ecf54e1c9e (diff) | |
| download | skiboot-04b200ce1eaaedaf425a49cc5369941fd837331d.zip skiboot-04b200ce1eaaedaf425a49cc5369941fd837331d.tar.gz skiboot-04b200ce1eaaedaf425a49cc5369941fd837331d.tar.bz2 | |
nvlink: Add fence mode emulation for NPUs
As NPUs are emulated PCI devices, they do not get physically fenced as real
PCI devices do. As such, when the device is in a state that it should be
fenced, we need to emulate this behaviour by returning all 1s in config
space reads.
This will be utilised by error injection in subsequent patches.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu.c')
| -rw-r--r-- | hw/npu.c | 15 |
1 files changed, 13 insertions, 2 deletions
@@ -390,6 +390,10 @@ static int64_t _npu_dev_cfg_read(struct phb *phb, uint32_t bdfn, /* Data returned upon errors */ *data = 0xffffffff; + /* If fenced, we want to return all 1s, so we're done. */ + if (p->fenced) + return OPAL_SUCCESS; + /* Retrieve NPU device */ dev = npu_dev_cfg_check(p, bdfn, offset, size); if (!dev) @@ -996,7 +1000,7 @@ static int64_t npu_freset(struct phb *phb __unused) return OPAL_SUCCESS; } -static int64_t npu_freeze_status(struct phb *phb __unused, +static int64_t npu_freeze_status(struct phb *phb, uint64_t pe_number __unused, uint8_t *freeze_state, uint16_t *pci_error_type __unused, @@ -1008,7 +1012,11 @@ static int64_t npu_freeze_status(struct phb *phb __unused, * introduce another PHB callback to translate it. For now, * it keeps the skiboot PCI enumeration going. */ - *freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN; + struct npu *p = phb_to_npu(phb); + if (p->fenced) + *freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE; + else + *freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN; return OPAL_SUCCESS; } @@ -1680,6 +1688,9 @@ static void npu_create_phb(struct dt_node *dn) p->xscom_base = dt_prop_get_u32(dn, "ibm,xscom-base"); p->total_devices = links; + /* TODO: When hardware fences are implemented, detect them here */ + p->fenced = false; + /* This is the AT base */ p->at_xscom = p->xscom_base + NPU_AT_SCOM_OFFSET; p->at_regs = (void *)dt_get_address(dn, 0, NULL); |