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author | Haren Myneni <haren@linux.vnet.ibm.com> | 2017-07-17 19:48:57 -0700 |
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committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-01 12:39:43 +1000 |
commit | 3b3c5962f432695ce48031381e12957a0726e83a (patch) | |
tree | d200cf9d9a0c3c52dcacfb8d0b145905ada89438 /hw/Makefile.inc | |
parent | b3623e67badbb7021900068e18b517dfd462009b (diff) | |
download | skiboot-3b3c5962f432695ce48031381e12957a0726e83a.zip skiboot-3b3c5962f432695ce48031381e12957a0726e83a.tar.gz skiboot-3b3c5962f432695ce48031381e12957a0726e83a.tar.bz2 |
NX: Add P9 NX support for 842 compression engine
This patch adds changes needed for 842 compression engine on power 9.
Virtual Accelerator Switch (VAS) is used to access NX 842 engine on P9
and the channel setup will be done with receive FIFO. So RxFIFO
address, logical partition ID (lpid), process ID (pid) and thread ID
(tid) are used for this setup. p9 NX supports high and normal priority
FIFOs. skiboot is not involved to process data with 842 engine, but
configures User Mode Access Control (UMAC) noitify match register with
these values and export them to kernel with device-tree entries.
Also configure registers to setup and enable / disable the engine with
the appropriate registers. Creates the following device-tree entries to
provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid
values so that kernel can drive P9 NX 842 engine.
The following nodes are located under an xscom node:
/xscom@<xscom_addr>/nx@<nx_addr>
/ibm,842-high-fifo : High priority 842 RxFIFO
/ibm,842-normal-fifo : Normal priority 842 RxFIFO
Each RxFIFO node contains:
compatible : ibm,p9-nx-842
priority : High or Normal
rx-fifo-address : RxFIFO address
rx-fifo-size : RXFIFO size
lpid : 0xfff (1's for 12 bits set in UMAC notify
match register)
pid : 842 coprocessor type
tid : Counter for 842
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/Makefile.inc')
0 files changed, 0 insertions, 0 deletions