ATTN: Set up attention area to handle attention

At present CPU control area ntuple in SPIRA structure is NULL.
ATTN component in Service Processor side checks for this field and if its empty,
it logs hardcoded SRC (0xBB821410) and generates SYSDUMP. So we have 1 SRC for
all failure (assert call) from OPAL side. This makes difficult to debug the issue.

Service processor provides attention area interface (FIPS PHyp Attentions spec),
so that we can pass SRC and user data (error message) to service processor.
This will helps us identify different failures in OPAL.

This patch enables attention area and provides interface (update_sp_attn_area())
to add src and user data (error message) through assert macro.

Attention SRC format:
	1st byte - Opal src type
	2-4 bytes - Holds the address of the assert function call

Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 36 insertions, 0 deletions

diff --git a/hdata/spira.c b/hdata/spira.c
index 45c282c..3923bb5 100644
--- a/hdata/spira.c
+++ b/hdata/spira.c
@@ -23,6 +23,7 @@
 #include <ccan/str/str.h>
 #include <chip.h>
 #include <fsp-mdst-table.h>
+#include <fsp-attn.h>
 
 #include "hdata.h"
 #include "hostservices.h"
@@ -46,6 +47,34 @@ __section(".procin.data") struct proc_init_data proc_init_data = {
 	},
 };
 
+__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area;
+__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1;
+__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2;
+__section(".cpuctrl.data") struct hsr_data_area cpu_ctl_hsr_area;
+
+__section(".cpuctrl.data") struct cpu_ctl_init_data cpu_ctl_init_data = {
+	.hdr = HDIF_SIMPLE_HDR(CPU_CTL_HDIF_SIG, 2, struct cpu_ctl_init_data),
+	.cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), sizeof(struct cpu_ctl_legacy_table)),
+	.cpu_ctl_lt = {
+		.spat = {
+			.addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_spat_area) + SKIBOOT_BASE),
+			.size = CPU_TO_BE64(sizeof(struct sp_addr_table)),
+		},
+		.sp_attn_area1 = {
+			.addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area1) + SKIBOOT_BASE),
+			.size = CPU_TO_BE64(sizeof(struct sp_attn_area)),
+		},
+		.sp_attn_area2 = {
+			.addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area2) + SKIBOOT_BASE),
+			.size = CPU_TO_BE64(sizeof(struct sp_attn_area)),
+		},
+		.hsr_area = {
+			.addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_hsr_area) + SKIBOOT_BASE),
+			.size = CPU_TO_BE64(sizeof(struct hsr_data_area)),
+		},
+	},
+};
+
 /* Populate MDST table
  *
  * Note that we only pass sapphire console buffer here so that we can
@@ -104,6 +133,13 @@ __section(".spira.data") struct spira spira = {
 			.alloc_len	=
 				CPU_TO_BE32(sizeof(init_mdst_table)),
 		},
+		.cpu_ctrl = {
+			.addr		= CPU_TO_BE64((unsigned long)&cpu_ctl_init_data),
+			.alloc_cnt	= CPU_TO_BE16(1),
+			.act_cnt	= CPU_TO_BE16(1),
+			.alloc_len	=
+					CPU_TO_BE32(sizeof(cpu_ctl_init_data)),
+		},
 	},
 };