phb3: Trick to allow control of the PCIe link width and speed

This implements a hook inside OPAL that catches 16 and 32 bit writes
to the link status register of the PHB.

It allows you to write a new speed or a new width, and OPAL will then
cause the PHB to renegociate.

Example:

First read the link status on PHB4:

setpci -s 0004:00:00.0 0x5a.w
a103

It's at x16 Gen3 speed (8GT/s)

bits 0x0ff0 are the width and 0x000f the speed. The width can be
1 to 16 and the speed 1 to 3 (2.5, 5 and 8GT/s)

Then try to bring it down to 1x Gen1 :

setpci -s 0004:00:00.0 0x5a.w=0xa011

Observe the result in the PHB:

/ # lspci -s 0004:00:00.0 -vv
0004:00:00.0 PCI bridge: IBM Device 03dc (prog-if 00 [Normal decode])
   .../...
LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt+

And in the device:

/ # lspci -s 0004:01:00.0 -vv
 .../...
LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

0 files changed, 0 insertions, 0 deletions