diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2021-10-03 11:22:08 +1000 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:08:19 +0530 |
| commit | c5424f683ee3f8d07faeb87f41f4572c6afd67b1 (patch) | |
| tree | 93fb8fef98bbe52d296894ef6f326478da657943 /core | |
| parent | 98815f21e9f4724fca39371ddfc7deb027edd013 (diff) | |
| download | skiboot-c5424f683ee3f8d07faeb87f41f4572c6afd67b1.zip skiboot-c5424f683ee3f8d07faeb87f41f4572c6afd67b1.tar.gz skiboot-c5424f683ee3f8d07faeb87f41f4572c6afd67b1.tar.bz2 | |
Remove support for POWER8 DD1
This significantly simplifies the SLW code.
HILE is now always supported.
Reviewed-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cpu.c | 23 |
1 files changed, 9 insertions, 14 deletions
@@ -35,7 +35,6 @@ unsigned int cpu_thread_count; unsigned int cpu_max_pir; struct cpu_thread *boot_cpu; static struct lock reinit_lock = LOCK_UNLOCKED; -static bool hile_supported; static bool radix_supported; static unsigned long hid0_hile; static unsigned long hid0_attn; @@ -1004,27 +1003,23 @@ void init_boot_cpu(void) case PVR_TYPE_P8E: case PVR_TYPE_P8: proc_gen = proc_gen_p8; - hile_supported = PVR_VERS_MAJ(mfspr(SPR_PVR)) >= 2; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; case PVR_TYPE_P8NVL: proc_gen = proc_gen_p8; - hile_supported = true; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; case PVR_TYPE_P9: case PVR_TYPE_P9P: proc_gen = proc_gen_p9; - hile_supported = true; radix_supported = true; hid0_hile = SPR_HID0_POWER9_HILE; hid0_attn = SPR_HID0_POWER9_ENABLE_ATTN; break; case PVR_TYPE_P10: proc_gen = proc_gen_p10; - hile_supported = true; radix_supported = true; hid0_hile = SPR_HID0_POWER10_HILE; hid0_attn = SPR_HID0_POWER10_ENABLE_ATTN; @@ -1061,6 +1056,11 @@ void init_boot_cpu(void) cpu_thread_count = 1; } + if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } + if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { prerror("CPU: POWER9N DD1 is not supported\n"); abort(); @@ -1602,7 +1602,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) } /* * Now we need to mark ourselves "active" or we'll be skipped - * by the various "for_each_active_..." calls done by slw_reinit() + * by the various "for_each_active_..." */ this_cpu()->state = cpu_state_active; this_cpu()->in_reinit = true; @@ -1616,10 +1616,8 @@ static int64_t opal_reinit_cpus(uint64_t flags) */ cpu_cleanup_all(); - /* If HILE change via HID0 is supported ... */ - if (hile_supported && - (flags & (OPAL_REINIT_CPUS_HILE_BE | - OPAL_REINIT_CPUS_HILE_LE))) { + if (flags & (OPAL_REINIT_CPUS_HILE_BE | + OPAL_REINIT_CPUS_HILE_LE)) { bool hile = !!(flags & OPAL_REINIT_CPUS_HILE_LE); flags &= ~(OPAL_REINIT_CPUS_HILE_BE | OPAL_REINIT_CPUS_HILE_LE); @@ -1674,10 +1672,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) rc = OPAL_SUCCESS; } - /* Handle P8 DD1 SLW reinit */ - if (flags != 0 && proc_gen == proc_gen_p8 && !hile_supported) - rc = slw_reinit(flags); - else if (flags != 0) + if (flags != 0) rc = OPAL_UNSUPPORTED; /* And undo the above */ |